blas_dot2_v01a/000755 000765 000024 00000000000 13532660317 014571 5ustar00mukunokistaff000000 000000 blas_dot2_v01a/make.inc000644 000765 000024 00000001143 13532136273 016177 0ustar00mukunokistaff000000 000000 ############################################## #--- PATH ------------------------------------ HOME = /home/mukunoki CUDA_PATH = /usr/local/cuda-10.0 CUDA_LDFLAGS = -L$(CUDA_PATH)/lib64 CUDA_INC = -I$(CUDA_PATH)/include #--- Compute Capability ---------------------- CC60 = no CC61 = no CC62 = no CC70 = no CC6070 = yes #--- Precision ------------------------------- PREC_S = yes PREC_D = yes PREC_SX = yes PREC_DX = yes #--- Routine --------------------------------- # level-1 DOT = yes # level-2 GEMV = yes CSRMV = yes # level-3 GEMM = yes ############################################## blas_dot2_v01a/Makefile000644 000765 000024 00000000355 13531160667 016236 0ustar00mukunokistaff000000 000000 MAKE = make #--no-print-directory MAKE_DIRS = src testing default: @for subdir in $(MAKE_DIRS) ; do \ (cd $$subdir && $(MAKE)) ;\ done clean: @for subdir in $(MAKE_DIRS) ; do \ (cd $$subdir && $(MAKE) clean) ;\ done blas_dot2_v01a/include/000755 000765 000024 00000000000 13532136664 016217 5ustar00mukunokistaff000000 000000 blas_dot2_v01a/testing/000755 000765 000024 00000000000 13532660244 016245 5ustar00mukunokistaff000000 000000 blas_dot2_v01a/lib/000755 000765 000024 00000000000 13532660233 015334 5ustar00mukunokistaff000000 000000 blas_dot2_v01a/eval_jcam2019/000755 000765 000024 00000000000 13532660076 017030 5ustar00mukunokistaff000000 000000 blas_dot2_v01a/src/000755 000765 000024 00000000000 13532660233 015355 5ustar00mukunokistaff000000 000000 blas_dot2_v01a/src/prec_sx.h000644 000765 000024 00000024506 13532136512 017176 0ustar00mukunokistaff000000 000000 #ifndef PREC_SX_H #define PREC_SX_H #ifdef PREC_SX // host #define MUBLAS_CSRMV mublasSXcsrmv #define MUBLAS_GEMM mublasSXgemm #define MUBLAS_GEMV mublasSXgemv #define MUBLAS_DOT mublasSXdot #define CUSPARSE_CSRMV cusparseScsrmv #define CUBLAS_GEMM cublasSgemm #define CUBLAS_GEMV cublasSgemv #define CUBLAS_DOT cublasSdot #define TYPE0 float #define ZERO0 0. #define ONE0 1. #define NEGONE0 -1. #define LOAD0(A) (A) // vec1 #define VEC1 1 #define TYPE1 double #define ZERO1 ZERO0 #define ONE1 ONE0 #define ADD1(A,B) __dadd_rn((A),(B)) #define MUL1(A,B) __dmul_rn((A),(B)) #define MAD1(A,B,C) __fma_rn((A),(B),(C)) #define LOAD1___ ld_global_f32_f64 #define LOAD1_NC ld_global_nc_f32_f64 #define STORE1___ st_global_f64_f32 #define STORE1_ATOMIC st_global_atomic_f64_f32 // vec2 #define VEC2 1 #define TYPE2 double2 #define ZERO2 make_double2(0.,0.) #define ONE2 make_double2(1.,1.) #define ADD2 cuDadd2 #define MUL12 cuDmul12 #define MAD122 cuDmad122 #define MAD212 cuDmad212 #define MAD2 cuDmad2 #define LOAD2___ ld_global_v2_f32_f64 #define LOAD2_NC ld_global_nc_v2_f32_f64 #define STORE2___ st_global_v2_f64_f32 #define STORE2_ATOMIC st_global_atomic_v2_f64_f32 // vec4 #define VEC4 0 #define TYPE4 float4 #define ZERO4 make_float4(0.,0.,0.,0.) #define ADD4 cuSadd4 #define ADD4RU cuSadd4ru #define SUB4 cuSsub4 #define SUB4RU cuSsub4ru #define MUL14 cuSmul14 #define MUL14RU cuSmul14ru #define MUL14RD cuSmul14rd #define MAD144 cuSmad144 #define MAD144RU cuSmad144ru #define MAD144RD cuSmad144rd #define MAD414 cuSmad414 #define MAD414RU cuSmad414ru #define MAD414RD cuSmad414rd #define MAD4 cuSmad4 #define LOAD4___ ld_global_v4_f32 #define LOAD4_NC ld_global_nc_v4_f32 #define STORE4___ st_global_v4_f32 #define STORE4_ATOMIC st_global_atomic_v4_f32 #endif // === Shuffle ===================================================== __device__ __forceinline__ void shuffleAdd (double &val, const int n) { #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 300) val += __hiloint2double( __shfl_xor_sync(0xFFFFFFFF, __double2hiint(val), n, WrpSize), __shfl_xor_sync(0xFFFFFFFF, __double2loint(val), n, WrpSize)); #endif } __device__ __forceinline__ float shuffleGet (float &val, const int n) { #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 300) return __shfl_xor_sync (0xFFFFFFFF, val, n, WrpSize); #endif } // ================================================================= // === Load ======================================================== // ld_global_f32 __device__ __forceinline__ void ld_global_v4_f32 (float4 ®, const float *addr) { #if USE_INLINE_ASM asm ("ld.global.v4.f32 {%0,%1,%2,%3}, [%4];": "=f"(reg.x), "=f"(reg.y), "=f"(reg.z), "=f"(reg.w): "l"(addr)); #else reg = (float4&)*addr; #endif } __device__ __forceinline__ void ld_global_v2_f32_f64 (double2 ®, const float *addr) { float2 t; #if USE_INLINE_ASM asm ("ld.global.v2.f32 {%0,%1}, [%2];": "=f"(t.x), "=f"(t.y): "l"(addr)); #else t = (float2&)*addr; #endif reg.x = (double)t.x; reg.y = (double)t.y; } __device__ __forceinline__ void ld_global_v2_f32 (float2 ®, const float *addr) { #if USE_INLINE_ASM asm ("ld.global.v2.f32 {%0,%1}, [%2];": "=f"(reg.x), "=f"(reg.y): "l"(addr)); #else reg = (float2&)*addr; #endif } __device__ __forceinline__ void ld_global_f32_f64 (double ®, const float *addr) { float t; #if USE_INLINE_ASM asm ("ld.global.f32 %0, [%1];": "=f"(t): "l"(addr)); #else t = *addr; reg = (double)t; #endif } __device__ __forceinline__ void ld_global_f32 (float ®, const float *addr) { #if USE_INLINE_ASM asm ("ld.global.f32 %0, [%1];": "=f"(reg): "l"(addr)); #else reg = *addr; #endif } // ld_global_nc_f32 __device__ __forceinline__ void ld_global_nc_v4_f32 (float4 ®, const float *addr) { #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.v4.f32 {%0,%1,%2,%3}, [%4];": "=f"(reg.x), "=f"(reg.y), "=f"(reg.z), "=f"(reg.w): "l"(addr)); #else asm ("ld.global.v4.f32 {%0,%1,%2,%3}, [%4];": "=f"(reg.x), "=f"(reg.y), "=f"(reg.z), "=f"(reg.w): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) reg = __ldg((float4*)addr); #else reg = (float4&)*addr; #endif #endif } __device__ __forceinline__ void ld_global_nc_v2_f32 (float2 ®, const float *addr) { #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.v2.f32 {%0,%1}, [%2];": "=f"(reg.x), "=f"(reg.y): "l"(addr)); #else asm ("ld.global.v2.f32 {%0,%1}, [%2];": "=f"(reg.x), "=f"(reg.y): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) reg = __ldg((float2*)addr); #else reg = (float2&)*addr; #endif #endif } __device__ __forceinline__ void ld_global_nc_v2_f32_f64 (double2 ®, const float *addr) { float2 t; #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.v2.f32 {%0,%1}, [%2];": "=f"(t.x), "=f"(t.y): "l"(addr)); #else asm ("ld.global.v2.f32 {%0,%1}, [%2];": "=f"(t.x), "=f"(t.y): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) t = __ldg((float2*)addr); #else t = (float2&)*addr; #endif #endif reg.x = (double)t.x; reg.y = (double)t.y; } __device__ __forceinline__ void ld_global_nc_f32 (float ®, const float *addr) { #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.f32 %0, [%1];": "=f"(reg): "l"(addr)); #else asm ("ld.global.f32 %0, [%1];": "=f"(reg): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) reg = __ldg(addr); #else reg = *addr; #endif #endif } __device__ __forceinline__ void ld_global_nc_f32_f64 (double ®, const float *addr) { float t; #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.f32 %0, [%1];": "=f"(t): "l"(addr)); #else asm ("ld.global.f32 %0, [%1];": "=f"(t): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) t = __ldg(addr); #else t = *addr; #endif #endif reg = (double)t; } // ld_shared_f32 __device__ __forceinline__ void ld_shared_v4_f32 (float4 ®, const float4 *addr) { #if USE_INLINE_ASM asm ("ld.shared.v4.f32 {%0,%1,%2,%3}, [%4];": "=f"(reg.x), "=f"(reg.y), "=f"(reg.z), "=f"(reg.w): "l"(addr)); #else reg = *addr; #endif } // ================================================================= // === Store ======================================================= __device__ __forceinline__ void st_global_v4_f32 (float *addr, const float4 reg) { #if USE_INLINE_ASM asm ("st.global.v4.f32 [%0], {%1,%2,%3,%4};":: "l"(addr), "f"(reg.x), "f"(reg.y), "f"(reg.z), "f"(reg.w)); #else (float4&)*addr = reg; #endif } __device__ __forceinline__ void st_global_v2_f32 (float *addr, const float2 reg) { #if USE_INLINE_ASM asm ("st.global.v2.f32 [%0], {%1,%2};":: "l"(addr), "f"(reg.x), "f"(reg.y)); #else (float2&)*addr = reg; #endif } __device__ __forceinline__ void st_global_v2_f64_f32 (float *addr, const double2 reg) { float2 t; t.x = (float)reg.x; t.y = (float)reg.y; #if USE_INLINE_ASM asm ("st.global.v2.f32 [%0], {%1,%2};":: "l"(addr), "f"(t.x), "f"(t.y)); #else (float2&)*addr = t; #endif } __device__ __forceinline__ void st_global_f32 (float *addr, const float reg) { #if USE_INLINE_ASM asm ("st.global.f32 [%0], %1;":: "l"(addr), "f"(reg)); #else *addr = reg; #endif } __device__ __forceinline__ void st_global_f64_f32 (float *addr, const double reg) { float t; t = (float)reg; #if USE_INLINE_ASM asm ("st.global.f32 [%0], %1;":: "l"(addr), "f"(reg)); #else *addr = t; #endif } __device__ __forceinline__ void st_global_atomic_v4_f32 (float *addr, const float4 reg) { atomicAdd (addr+0, reg.x); atomicAdd (addr+4, reg.y); atomicAdd (addr+8, reg.z); atomicAdd (addr+16, reg.w); } __device__ __forceinline__ void st_global_atomic_v2_f32 (float *addr, const float2 reg) { atomicAdd (addr+0, reg.x); atomicAdd (addr+4, reg.y); } __device__ __forceinline__ void st_global_atomic_f32 (float *addr, const float reg) { atomicAdd (addr, reg); } // ================================================================= // === Vector ====================================================== __device__ __forceinline__ float2 cuSadd2 (const float2 a, const float2 b) { return make_float2 (a.x+b.x, a.y+b.y); } __device__ __forceinline__ float2 cuSmul12 (const float a, const float2 b) { return make_float2 (a*b.x, a*b.y); } __device__ __forceinline__ float2 cuSmad122 (const float a, const float2 b, const float2 c) { return make_float2 (a*b.x+c.x, a*b.y+c.y); } __device__ __forceinline__ float2 cuSmad212 (const float2 a, const float b, const float2 c) { return make_float2 (a.x*b+c.x, a.y*b+c.y); } __device__ __forceinline__ float2 cuSmad2 (const float2 a, const float2 b, const float2 c) { return make_float2 (a.x*b.x+c.x, a.y*b.y+c.y); } __device__ __forceinline__ float4 cuSadd4 (const float4 a, const float4 b) { return make_float4 (a.x+b.x, a.y+b.y, a.z+b.z, a.w+b.w); } __device__ __forceinline__ float4 cuSsub4 (const float4 a, const float4 b) { return make_float4 (a.x-b.x, a.y-b.y, a.z-b.z, a.w-b.w); } __device__ __forceinline__ float4 cuSmul14 (const float a, const float4 b) { return make_float4 (a*b.x, a*b.y, a*b.z, a*b.w); } __device__ __forceinline__ float4 cuSmad144 (const float a, const float4 b, const float4 c) { return make_float4 (a*b.x+c.x, a*b.y+c.y, a*b.z+c.z, a*b.w+c.w); } __device__ __forceinline__ float4 cuSmad414 (const float4 a, const float b, const float4 c) { return make_float4 (a.x*b+c.x, a.y*b+c.y, a.z*b+c.z, a.w*b+c.w); } __device__ __forceinline__ float4 cuSmad4 (const float4 a, const float4 b, const float4 c) { return make_float4 (a.x*b.x+c.x, a.y*b.y+c.y, a.z*b.z+c.z, a.w*b.w+c.w); } __device__ __forceinline__ double2 cuDadd2 (const double2 a, const double2 b) { return make_double2 (a.x+b.x, a.y+b.y); } __device__ __forceinline__ double2 cuDmul12 (const double a, const double2 b) { return make_double2 (a*b.x, a*b.y); } __device__ __forceinline__ double2 cuDmad2 (const double2 a, const double2 b, const double2 c) { return make_double2 (a.x*b.x+c.x, a.y*b.y+c.y); } __device__ __forceinline__ double2 cuDmad122 (const double a, const double2 b, const double2 c) { return make_double2 (a*b.x+c.x, a*b.y+c.y); } __device__ __forceinline__ double2 cuDmad212 (const double2 a, const double b, const double2 c) { return make_double2 (a.x*b+c.x, a.y*b+c.y); } // ================================================================= #endif blas_dot2_v01a/src/mublas_gemm_nn_kernel.cu000644 000765 000024 00000030761 13532475277 022254 0ustar00mukunokistaff000000 000000 #include "mublas_devel.h" #define USE_NC_A_GEMM_NN 1 #define USE_NC_B_GEMM_NN 1 /* *********************************************** Macro *********************************************** */ #if USE_NC_A_GEMM_NN #define RESTRICT_A __restrict__ #define LOAD1_A LOAD1_NC #define LOAD2_A LOAD2_NC #define LOAD4_A LOAD4_NC #else #define RESTRICT_A #define LOAD1_A LOAD1___ #define LOAD2_A LOAD2___ #define LOAD4_A LOAD4___ #endif #if USE_NC_B_GEMM_NN #define RESTRICT_B __restrict__ #define LOAD1_B LOAD1_NC #define LOAD2_B LOAD2_NC #define LOAD4_B LOAD4_NC #else #define RESTRICT_B #define LOAD1_B LOAD1___ #define LOAD2_B LOAD2___ #define LOAD4_B LOAD4___ #endif #define LOAD1_C LOAD1___ #define LOAD2_C LOAD2___ #define STORE1_C STORE1___ #define STORE2_C STORE2___ /* *********************************************** Functions for determining Tx and Ty *********************************************** */ __host__ __inline__ void getBlkPerGrd_GEMM_NN_rb1x1 (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; const SIZE_T Bm = mh->Tx; const SIZE_T Bn = mh->Ty; mh->Bx = ceilingEx ((float)mh->m / (float)Bm, 1); mh->By = ceilingEx ((float)mh->n / (float)Bn, 1); mh->Bz = 1; } __host__ __inline__ void getShmPerBlk_GEMM_NN_rb1x1 (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; const SIZE_T Bm = mh->Tx; const SIZE_T Bn = mh->Ty; const SIZE_T Bk = mh->Tx; const SIZE_T ShmUse = Bm * Bk + Bk * Bn; mh->ShmPerBlk = ceilingEx ((float)(ShmUse * mh->N_one), mh->ShmUnit); } __host__ __inline__ void getBlkPerGrd_GEMM_NN_rb2x2 (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; const SIZE_T Bm = mh->Tx * 2; const SIZE_T Bn = mh->Ty * 2; mh->Bx = ceilingEx ((float)mh->m / (float)Bm, 1); mh->By = ceilingEx ((float)mh->n / (float)Bn, 1); } __host__ __inline__ void getShmPerBlk_GEMM_NN_rb2x2 (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; const SIZE_T Bm = mh->Tx * 2; const SIZE_T Bn = mh->Ty * 2; const SIZE_T Bk = mh->Tx; const SIZE_T ShmUse = Bm * Bk + Bk * Bn; mh->ShmPerBlk = ceilingEx ((float)(ShmUse * mh->N_one), mh->ShmUnit); } __host__ __inline__ void getBlkPerGrd_GEMM_NN_rb4x4 (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; const SIZE_T Bm = mh->Tx * 4; const SIZE_T Bn = mh->Ty * 4; mh->Bx = ceilingEx ((float)mh->m / (float)Bm, 1); mh->By = ceilingEx ((float)mh->n / (float)Bn, 1); } __host__ __inline__ void getShmPerBlk_GEMM_NN_rb4x4 (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; const SIZE_T Bm = mh->Tx * 4; const SIZE_T Bn = mh->Ty * 4; const SIZE_T Bk = mh->Tx; const SIZE_T ShmUse = Bm * Bk + Bk * Bn; mh->ShmPerBlk = ceilingEx ((float)(ShmUse * mh->N_one), mh->ShmUnit); } __host__ __inline__ void getBlkPerGrd_GEMM_NN_rb8x8 (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; const SIZE_T Bm = mh->Tx * 8; const SIZE_T Bn = mh->Ty * 8; mh->Bx = ceilingEx ((float)mh->m / (float)Bm, 1); mh->By = ceilingEx ((float)mh->n / (float)Bn, 1); } __host__ __inline__ void getShmPerBlk_GEMM_NN_rb8x8 (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; const SIZE_T Bm = mh->Tx * 8; const SIZE_T Bn = mh->Ty * 8; const SIZE_T Bk = mh->Tx; const SIZE_T ShmUse = Bm * Bk + Bk * Bn; #ifdef PREC_SX mh->ShmPerBlk = ceilingEx ((float)(ShmUse * mh->N_one * 2), mh->ShmUnit); #else mh->ShmPerBlk = ceilingEx ((float)(ShmUse * mh->N_one), mh->ShmUnit); #endif } __global__ void MUBLAS_GEMM_NN_DEVICE_tb8x8_rb8x8_v4_maxwell ( const SIZE_T m, const SIZE_T n, const SIZE_T k, const TYPE0 alpha, const TYPE0 * RESTRICT_A Ag, const SIZE_T lda, const TYPE0 * RESTRICT_B Bg, const SIZE_T ldb, const TYPE0 beta, TYPE0 *Cg, const SIZE_T ldc ) { #if VEC4 int32_t i, j, jk, ki; const int32_t iBx = blockIdx.x; const int32_t iBy = blockIdx.y; const int32_t iTx = threadIdx.x; const int32_t iTy = threadIdx.y; const int32_t addrx = iBx*64+iTx*4; const int32_t addry = iBy*64+iTy*8; __shared__ TYPE4 As4[8][16+1]; __shared__ TYPE4 Bs4[8][16+1]; register TYPE4 Tr4[8][2]; register TYPE4 Ar4[2]; register TYPE4 Br4[2]; register TYPE4 Cr4[2]; const TYPE0 * addrAg = &Ag[iTy*lda + addrx]; const TYPE0 * addrBg = &Bg[addry*ldb + iTx]; const TYPE0 * addrCg = &Cg[addry*ldc + addrx]; #pragma unroll for (j = 0; j < 8; j++) #pragma unroll for (i = 0; i < 2; i++) Tr4[j][i] = ZERO4; for (jk = 0; jk < k; jk += 8) { LOAD4_A (As4[iTy][iTx+0], addrAg+0); LOAD4_A (As4[iTy][iTx+8], addrAg+32); LOAD1_B (Br4[0].x, addrBg+0*ldb); LOAD1_B (Br4[0].y, addrBg+1*ldb); LOAD1_B (Br4[0].z, addrBg+2*ldb); LOAD1_B (Br4[0].w, addrBg+3*ldb); LOAD1_B (Br4[1].x, addrBg+4*ldb); LOAD1_B (Br4[1].y, addrBg+5*ldb); LOAD1_B (Br4[1].z, addrBg+6*ldb); LOAD1_B (Br4[1].w, addrBg+7*ldb); Bs4[iTx][iTy*2+0] = Br4[0]; Bs4[iTx][iTy*2+1] = Br4[1]; __syncthreads (); #pragma unroll for (ki = 0; ki < 8; ki++) { Ar4[0] = As4[ki][iTx+0]; Ar4[1] = As4[ki][iTx+8]; Br4[0] = Bs4[ki][iTy*2+0]; Br4[1] = Bs4[ki][iTy*2+1]; Tr4[0][0] = MAD414 (Ar4[0], Br4[0].x, Tr4[0][0]); Tr4[1][0] = MAD414 (Ar4[0], Br4[0].y, Tr4[1][0]); Tr4[2][0] = MAD414 (Ar4[0], Br4[0].z, Tr4[2][0]); Tr4[3][0] = MAD414 (Ar4[0], Br4[0].w, Tr4[3][0]); Tr4[4][0] = MAD414 (Ar4[0], Br4[1].x, Tr4[4][0]); Tr4[5][0] = MAD414 (Ar4[0], Br4[1].y, Tr4[5][0]); Tr4[6][0] = MAD414 (Ar4[0], Br4[1].z, Tr4[6][0]); Tr4[7][0] = MAD414 (Ar4[0], Br4[1].w, Tr4[7][0]); Tr4[0][1] = MAD414 (Ar4[1], Br4[0].x, Tr4[0][1]); Tr4[1][1] = MAD414 (Ar4[1], Br4[0].y, Tr4[1][1]); Tr4[2][1] = MAD414 (Ar4[1], Br4[0].z, Tr4[2][1]); Tr4[3][1] = MAD414 (Ar4[1], Br4[0].w, Tr4[3][1]); Tr4[4][1] = MAD414 (Ar4[1], Br4[1].x, Tr4[4][1]); Tr4[5][1] = MAD414 (Ar4[1], Br4[1].y, Tr4[5][1]); Tr4[6][1] = MAD414 (Ar4[1], Br4[1].z, Tr4[6][1]); Tr4[7][1] = MAD414 (Ar4[1], Br4[1].w, Tr4[7][1]); } __syncthreads (); addrAg += 8*lda; addrBg += 8; } if (alpha == ONE0 && beta == ZERO0) { #pragma unroll for (j = 0; j < 8; j++) { (TYPE4&)*(addrCg+ 0) = Tr4[j][0]; (TYPE4&)*(addrCg+32) = Tr4[j][1]; addrCg += ldc; } } else { #pragma unroll for (j = 0; j < 8; j++) { Cr4[0] = (TYPE4&)*(addrCg+ 0); Cr4[1] = (TYPE4&)*(addrCg+32); Cr4[0] = MAD144 (alpha, Tr4[j][0], MUL14 (beta, Cr4[0])); Cr4[1] = MAD144 (alpha, Tr4[j][1], MUL14 (beta, Cr4[1])); (TYPE4&)*(addrCg+ 0) = Cr4[0]; (TYPE4&)*(addrCg+32) = Cr4[1]; addrCg += ldc; } } #endif } __global__ void MUBLAS_GEMM_NN_DEVICE_tb8x8_rb8x8_v2_maxwell ( const SIZE_T m, const SIZE_T n, const SIZE_T k, const TYPE0 alpha, const TYPE0 * RESTRICT_A Ag, const SIZE_T lda, const TYPE0 * RESTRICT_B Bg, const SIZE_T ldb, const TYPE0 beta, TYPE0 *Cg, const SIZE_T ldc ) { #if VEC2 int32_t i, j, jk, ki; const int32_t iBx = blockIdx.x; const int32_t iBy = blockIdx.y; const int32_t iTx = threadIdx.x; const int32_t iTy = threadIdx.y; const int32_t addrx = iBx*64+iTx*2; const int32_t addry = iBy*64+iTy*8; __shared__ TYPE2 As2[8][32+1]; __shared__ TYPE2 Bs2[8][32+1]; register TYPE2 Tr2[8][4]; register TYPE2 Ar2[4]; register TYPE2 Br2[4]; register TYPE2 Cr2[4]; const TYPE0 * addrAg = &Ag[iTy*lda + addrx]; const TYPE0 * addrBg = &Bg[addry*ldb + iTx]; TYPE0 * addrCg = &Cg[addry*ldc + addrx]; #pragma unroll for (j = 0; j < 8; j++) #pragma unroll for (i = 0; i < 4; i++) Tr2[j][i] = ZERO2; for (jk = 0; jk < k; jk += 8) { LOAD2_A (As2[iTy][iTx+0], addrAg+0); LOAD2_A (As2[iTy][iTx+8], addrAg+16); LOAD2_A (As2[iTy][iTx+16], addrAg+32); LOAD2_A (As2[iTy][iTx+24], addrAg+48); LOAD1_B (Br2[0].x, addrBg+0*ldb); LOAD1_B (Br2[0].y, addrBg+1*ldb); LOAD1_B (Br2[1].x, addrBg+2*ldb); LOAD1_B (Br2[1].y, addrBg+3*ldb); LOAD1_B (Br2[2].x, addrBg+4*ldb); LOAD1_B (Br2[2].y, addrBg+5*ldb); LOAD1_B (Br2[3].x, addrBg+6*ldb); LOAD1_B (Br2[3].y, addrBg+7*ldb); Bs2[iTx][iTy*4+0] = Br2[0]; Bs2[iTx][iTy*4+1] = Br2[1]; Bs2[iTx][iTy*4+2] = Br2[2]; Bs2[iTx][iTy*4+3] = Br2[3]; __syncthreads (); #pragma unroll for (ki = 0; ki < 8; ki++) { Ar2[0] = As2[ki][iTx+0]; Ar2[1] = As2[ki][iTx+8]; Ar2[2] = As2[ki][iTx+16]; Ar2[3] = As2[ki][iTx+24]; Br2[0] = Bs2[ki][iTy*4+0]; Br2[1] = Bs2[ki][iTy*4+1]; Br2[2] = Bs2[ki][iTy*4+2]; Br2[3] = Bs2[ki][iTy*4+3]; Tr2[0][0] = MAD212 (Ar2[0], Br2[0].x, Tr2[0][0]); Tr2[1][0] = MAD212 (Ar2[0], Br2[0].y, Tr2[1][0]); Tr2[2][0] = MAD212 (Ar2[0], Br2[1].x, Tr2[2][0]); Tr2[3][0] = MAD212 (Ar2[0], Br2[1].y, Tr2[3][0]); Tr2[4][0] = MAD212 (Ar2[0], Br2[2].x, Tr2[4][0]); Tr2[5][0] = MAD212 (Ar2[0], Br2[2].y, Tr2[5][0]); Tr2[6][0] = MAD212 (Ar2[0], Br2[3].x, Tr2[6][0]); Tr2[7][0] = MAD212 (Ar2[0], Br2[3].y, Tr2[7][0]); Tr2[0][1] = MAD212 (Ar2[1], Br2[0].x, Tr2[0][1]); Tr2[1][1] = MAD212 (Ar2[1], Br2[0].y, Tr2[1][1]); Tr2[2][1] = MAD212 (Ar2[1], Br2[1].x, Tr2[2][1]); Tr2[3][1] = MAD212 (Ar2[1], Br2[1].y, Tr2[3][1]); Tr2[4][1] = MAD212 (Ar2[1], Br2[2].x, Tr2[4][1]); Tr2[5][1] = MAD212 (Ar2[1], Br2[2].y, Tr2[5][1]); Tr2[6][1] = MAD212 (Ar2[1], Br2[3].x, Tr2[6][1]); Tr2[7][1] = MAD212 (Ar2[1], Br2[3].y, Tr2[7][1]); Tr2[0][2] = MAD212 (Ar2[2], Br2[0].x, Tr2[0][2]); Tr2[1][2] = MAD212 (Ar2[2], Br2[0].y, Tr2[1][2]); Tr2[2][2] = MAD212 (Ar2[2], Br2[1].x, Tr2[2][2]); Tr2[3][2] = MAD212 (Ar2[2], Br2[1].y, Tr2[3][2]); Tr2[4][2] = MAD212 (Ar2[2], Br2[2].x, Tr2[4][2]); Tr2[5][2] = MAD212 (Ar2[2], Br2[2].y, Tr2[5][2]); Tr2[6][2] = MAD212 (Ar2[2], Br2[3].x, Tr2[6][2]); Tr2[7][2] = MAD212 (Ar2[2], Br2[3].y, Tr2[7][2]); Tr2[0][3] = MAD212 (Ar2[3], Br2[0].x, Tr2[0][3]); Tr2[1][3] = MAD212 (Ar2[3], Br2[0].y, Tr2[1][3]); Tr2[2][3] = MAD212 (Ar2[3], Br2[1].x, Tr2[2][3]); Tr2[3][3] = MAD212 (Ar2[3], Br2[1].y, Tr2[3][3]); Tr2[4][3] = MAD212 (Ar2[3], Br2[2].x, Tr2[4][3]); Tr2[5][3] = MAD212 (Ar2[3], Br2[2].y, Tr2[5][3]); Tr2[6][3] = MAD212 (Ar2[3], Br2[3].x, Tr2[6][3]); Tr2[7][3] = MAD212 (Ar2[3], Br2[3].y, Tr2[7][3]); } __syncthreads (); addrAg += 8*lda; addrBg += 8; } if (alpha == ONE0 && beta == ZERO0) { #pragma unroll for (j = 0; j < 8; j++) { STORE2_C (addrCg+ 0, Tr2[j][0]); STORE2_C (addrCg+16, Tr2[j][1]); STORE2_C (addrCg+32, Tr2[j][2]); STORE2_C (addrCg+48, Tr2[j][3]); addrCg += ldc; } } else { #pragma unroll for (j = 0; j < 8; j++) { LOAD2_C (Cr2[0], addrCg+ 0); LOAD2_C (Cr2[1], addrCg+16); LOAD2_C (Cr2[2], addrCg+32); LOAD2_C (Cr2[3], addrCg+48); Cr2[0] = MAD122 (alpha, Tr2[j][0], MUL12 (beta, Cr2[0])); Cr2[1] = MAD122 (alpha, Tr2[j][1], MUL12 (beta, Cr2[1])); Cr2[2] = MAD122 (alpha, Tr2[j][2], MUL12 (beta, Cr2[2])); Cr2[3] = MAD122 (alpha, Tr2[j][3], MUL12 (beta, Cr2[3])); STORE2_C (addrCg+ 0, Cr2[0]); STORE2_C (addrCg+16, Cr2[1]); STORE2_C (addrCg+32, Cr2[2]); STORE2_C (addrCg+48, Cr2[3]); addrCg += ldc; } } #endif } __global__ void MUBLAS_GEMM_NN_DEVICE_tb16x16_rb1x1_s1_maxwell ( const SIZE_T m, const SIZE_T n, const SIZE_T k, const TYPE0 alpha, const TYPE0 * RESTRICT_A Ag, const SIZE_T lda, const TYPE0 * RESTRICT_B Bg, const SIZE_T ldb, const TYPE0 beta, TYPE0 *Cg, const SIZE_T ldc ) { int32_t jk, ki; const int32_t iBx = blockIdx.x; const int32_t iBy = blockIdx.y; const int32_t iTx = threadIdx.x; const int32_t iTy = threadIdx.y; const int32_t addrx = iBx*16+iTx; const int32_t addry = iBy*16+iTy; __shared__ TYPE1 As1[16][16+1]; __shared__ TYPE1 Bs1[16][16+1]; register TYPE1 Ar1, Br1, Cr1, Tr1; TYPE0 * addrCg = &Cg[addry*ldc + addrx]; Tr1 = ZERO1; jk = 0; if (k > 16){ for (jk = 0; jk < k-16; jk += 16) { LOAD1_A (As1[iTy][iTx], &Ag[(jk+iTy)*lda + min(m-1,addrx)]); LOAD1_B (Br1, &Bg[min(n-1,addry)*ldb + (iTx+jk)]); Bs1[iTx][iTy] = Br1; __syncthreads (); #pragma unroll for (ki = 0; ki < 16; ki++) { Ar1 = As1[ki][iTx]; Br1 = Bs1[ki][iTy]; Tr1 = MAD1 (Ar1, Br1, Tr1); } __syncthreads (); } } { LOAD1_A (As1[iTy][iTx], &Ag[min(k-1,jk+iTy)*lda + min(m-1,addrx)]); LOAD1_B (Br1, &Bg[min(n-1,addry)*ldb + min(k-1,iTx+jk)]); Bs1[iTx][iTy] = Br1; __syncthreads (); #pragma unroll for (ki = 0; ki+jk < k; ki++) { Ar1 = As1[ki][iTx]; Br1 = Bs1[ki][iTy]; Tr1 = MAD1 (Ar1, Br1, Tr1); } __syncthreads (); } if (alpha == ONE0 && beta == ZERO0) { if (addrx < m && addry < n) STORE1_C (addrCg, Tr1); } else { if (addrx < m && addry < n) { LOAD1_C (Cr1, addrCg); Cr1 = MAD1 (LOAD0(alpha), Tr1, MUL1 (LOAD0(beta), Cr1)); STORE1_C (addrCg, Cr1); } } } #undef RESTRICT_A #undef RESTRICT_B #undef LOAD1_A #undef LOAD2_A #undef LOAD4_A #undef LOAD1_B #undef LOAD2_B #undef LOAD4_B #undef LOAD1_C #undef LOAD2_C #undef LOAD4_C #undef STORE1_C #undef STORE2_C #undef STORE4_C blas_dot2_v01a/src/mublas_csrmv.cu000644 000765 000024 00000002157 13532474641 020416 0ustar00mukunokistaff000000 000000 #include "mublas_devel.h" #include "mublas_csrmv_n_kernel.cu" __host__ int32_t MUBLAS_CSRMV ( mublasHandle_t* mh, const char trans, const size_t m, const size_t n, const size_t nnz, const TYPE0 *alpha, const TYPE0 *csrValA, const int32_t *csrRowPtrA, const int32_t *csrColIndA, const TYPE0 *x, const TYPE0 *beta, TYPE0 *y ) { void (*kernel) (const SIZE_T, const TYPE0, const TYPE0*, const int32_t*, const int32_t*, const TYPE0*, const TYPE0, TYPE0*); kernel = &MUBLAS_CSRMV_N_DEVICE_N32; mublasRecipeDefault (mh); #ifdef PREC_DX if (*alpha != ONE0 || *beta != ZERO0) { printf ("alpha!=1 (%f), beta!=0 (%f)\n", *alpha, *beta); return 0; } #endif if (trans == 'T' || trans == 't') { printf ("mublas error: not implemented"); return 0; } mh->m = m; mh->n = n; mh->N_one = sizeof (TYPE0); mh->N_T = 32; mh->BlkDim = 1; mh->func_getBlkPerGrd = &getBlkPerGrd_CSRMV_N; mh->Tx = 512; mh->Ty = 1; getBlkPerGrd_CSRMV_N (mh); dim3 threads = dim3 (mh->Tx, mh->Ty); dim3 grid = dim3 (mh->Bx, mh->By); kernel <<< grid, threads >>> (m, *alpha, csrValA, csrRowPtrA, csrColIndA, x, *beta, y); return 0; } blas_dot2_v01a/src/mublas_devel.h000644 000765 000024 00000002025 13532137340 020165 0ustar00mukunokistaff000000 000000 #ifndef MUBLAS_DEVEL_H #define MUBLAS_DEVEL_H #define SIZE_T size_t//int32_t #define USE_INLINE_ASM 0 #include #include #define __STDC_FORMAT_MACROS #include #include #include #include #define WrpSize 32 #define min(a, b) ((a) < (b) ? (a) : (b)) #define max(a, b) ((a) > (b) ? (a) : (b)) #include "../include/mublas.h" __host__ __inline__ size_t ceilingEx (const float n, const size_t c) { return (size_t)ceil(n/c)*c; } __host__ __inline__ size_t floorEx (const float n, const size_t c) { return (size_t)floor(n/c)*c; } extern __host__ void mublasRecipeDefault (mublasHandle_t* mh); extern __host__ void getOccupancies ( mublasHandle_t* mh); extern __host__ void mublas_optimizer (mublasHandle_t* mh); extern __host__ void getShmSize ( mublasHandle_t* mh); #ifdef PREC_S #include "prec_s.h" #endif #ifdef PREC_D #include "prec_d.h" #endif #ifdef PREC_DX #include "prec_dx.h" #endif #ifdef PREC_SX #include "prec_sx.h" #endif #endif blas_dot2_v01a/src/prec_s.h000644 000765 000024 00000016706 13532135604 017012 0ustar00mukunokistaff000000 000000 #ifndef PREC_S_H #define PREC_S_H #ifdef PREC_S // host #define MUBLAS_CSRMV mublasScsrmv #define MUBLAS_GEMM mublasSgemm #define MUBLAS_GEMV mublasSgemv #define MUBLAS_DOT mublasSdot #define CUSPARSE_CSRMV cusparseScsrmv #define CUBLAS_GEAM cublasSgeam #define CUBLAS_GEMM cublasSgemm #define CUBLAS_GEMV cublasSgemv #define CUBLAS_DOT cublasSdot #define TYPE0 float #define ZERO0 0. #define ONE0 1. #define NEGONE0 -1. #define LOAD0(A) (A) // vec1 #define VEC1 1 #define TYPE1 TYPE0 #define ZERO1 ZERO0 #define ONE1 ONE0 #define ADD1(A,B) ((A)+(B)) #define MUL1(A,B) ((A)*(B)) #define MAD1(A,B,C) (((A)*(B))+(C)) #define LOAD1___ ld_global_f32 #define LOAD1_NC ld_global_nc_f32 #define STORE1___ st_global_f32 #define STORE1_ATOMIC st_global_atomic_f32 // vec2 #define VEC2 1 #define TYPE2 float2 #define ZERO2 make_float2(0.,0.) #define ONE2 make_float2(1.,1.) #define ADD2 cuSadd2 #define MUL12 cuSmul12 #define MAD122 cuSmad122 #define MAD212 cuSmad212 #define MAD2 cuSmad2 #define LOAD2___ ld_global_v2_f32 #define LOAD2_NC ld_global_nc_v2_f32 #define STORE2___ st_global_v2_f32 #define STORE2_ATOMIC st_global_atomic_v2_f32 // vec4 #define VEC4 1 #define TYPE4 float4 #define ZERO4 make_float4(0.,0.,0.,0.) #define ADD4 cuSadd4 #define ADD4RU cuSadd4ru #define SUB4 cuSsub4 #define SUB4RU cuSsub4ru #define MUL14 cuSmul14 #define MUL14RU cuSmul14ru #define MUL14RD cuSmul14rd #define MAD144 cuSmad144 #define MAD144RU cuSmad144ru #define MAD144RD cuSmad144rd #define MAD414 cuSmad414 #define MAD414RU cuSmad414ru #define MAD414RD cuSmad414rd #define MAD4 cuSmad4 #define LOAD4___ ld_global_v4_f32 #define LOAD4_NC ld_global_nc_v4_f32 #define STORE4___ st_global_v4_f32 #define STORE4_ATOMIC st_global_atomic_v4_f32 #endif // === Shuffle ===================================================== __device__ __forceinline__ void shuffleAdd (float &val, const int n) { #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 300) val += __shfl_xor_sync (0xFFFFFFFF, val, n, WrpSize); #endif } // ================================================================= // === Load ======================================================== // ld_global_f32 __device__ __forceinline__ void ld_global_v4_f32 (float4 ®, const float *addr) { #if USE_INLINE_ASM asm ("ld.global.v4.f32 {%0,%1,%2,%3}, [%4];": "=f"(reg.x), "=f"(reg.y), "=f"(reg.z), "=f"(reg.w): "l"(addr)); #else reg = (float4&)*addr; #endif } __device__ __forceinline__ void ld_global_v2_f32 (float2 ®, const float *addr) { #if USE_INLINE_ASM asm ("ld.global.v2.f32 {%0,%1}, [%2];": "=f"(reg.x), "=f"(reg.y): "l"(addr)); #else reg = (float2&)*addr; #endif } __device__ __forceinline__ void ld_global_f32 (float ®, const float *addr) { #if USE_INLINE_ASM asm ("ld.global.f32 %0, [%1];": "=f"(reg): "l"(addr)); #else reg = *addr; #endif } // ld_global_nc_f32 __device__ __forceinline__ void ld_global_nc_v4_f32 (float4 ®, const float *addr) { #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.v4.f32 {%0,%1,%2,%3}, [%4];": "=f"(reg.x), "=f"(reg.y), "=f"(reg.z), "=f"(reg.w): "l"(addr)); #else asm ("ld.global.v4.f32 {%0,%1,%2,%3}, [%4];": "=f"(reg.x), "=f"(reg.y), "=f"(reg.z), "=f"(reg.w): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) reg = __ldg((float4*)addr); #else reg = (float4&)*addr; #endif #endif } __device__ __forceinline__ void ld_global_nc_v2_f32 (float2 ®, const float *addr) { #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.v2.f32 {%0,%1}, [%2];": "=f"(reg.x), "=f"(reg.y): "l"(addr)); #else asm ("ld.global.v2.f32 {%0,%1}, [%2];": "=f"(reg.x), "=f"(reg.y): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) reg = __ldg((float2*)addr); #else reg = (float2&)*addr; #endif #endif } __device__ __forceinline__ void ld_global_nc_f32 (float ®, const float *addr) { #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.f32 %0, [%1];": "=f"(reg): "l"(addr)); #else asm ("ld.global.f32 %0, [%1];": "=f"(reg): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) reg = __ldg(addr); #else reg = *addr; #endif #endif } // ld_shared_f32 __device__ __forceinline__ void ld_shared_v4_f32 (float4 ®, const float4 *addr) { #if USE_INLINE_ASM asm ("ld.shared.v4.f32 {%0,%1,%2,%3}, [%4];": "=f"(reg.x), "=f"(reg.y), "=f"(reg.z), "=f"(reg.w): "l"(addr)); #else reg = *addr; #endif } // ================================================================= // === Store ======================================================= __device__ __forceinline__ void st_global_v4_f32 (float *addr, const float4 reg) { #if USE_INLINE_ASM asm ("st.global.v4.f32 [%0], {%1,%2,%3,%4};":: "l"(addr), "f"(reg.x), "f"(reg.y), "f"(reg.z), "f"(reg.w)); #else (float4&)*addr = reg; #endif } __device__ __forceinline__ void st_global_v2_f32 (float *addr, const float2 reg) { #if USE_INLINE_ASM asm ("st.global.v2.f32 [%0], {%1,%2};":: "l"(addr), "f"(reg.x), "f"(reg.y)); #else (float2&)*addr = reg; #endif } __device__ __forceinline__ void st_global_f32 (float *addr, const float reg) { #if USE_INLINE_ASM asm ("st.global.f32 [%0], %1;":: "l"(addr), "f"(reg)); #else *addr = reg; #endif } __device__ __forceinline__ void st_global_atomic_v4_f32 (float *addr, const float4 reg) { atomicAdd (addr+0, reg.x); atomicAdd (addr+4, reg.y); atomicAdd (addr+8, reg.z); atomicAdd (addr+16, reg.w); } __device__ __forceinline__ void st_global_atomic_v2_f32 (float *addr, const float2 reg) { atomicAdd (addr+0, reg.x); atomicAdd (addr+4, reg.y); } __device__ __forceinline__ void st_global_atomic_f32 (float *addr, const float reg) { atomicAdd (addr, reg); } // ================================================================= // === Vector ====================================================== __device__ __forceinline__ float2 cuSadd2 (const float2 a, const float2 b) { return make_float2 (a.x+b.x, a.y+b.y); } __device__ __forceinline__ float2 cuSmul12 (const float a, const float2 b) { return make_float2 (a*b.x, a*b.y); } __device__ __forceinline__ float2 cuSmad122 (const float a, const float2 b, const float2 c) { return make_float2 (a*b.x+c.x, a*b.y+c.y); } __device__ __forceinline__ float2 cuSmad212 (const float2 a, const float b, const float2 c) { return make_float2 (a.x*b+c.x, a.y*b+c.y); } __device__ __forceinline__ float2 cuSmad2 (const float2 a, const float2 b, const float2 c) { return make_float2 (a.x*b.x+c.x, a.y*b.y+c.y); } __device__ __forceinline__ float4 cuSadd4 (const float4 a, const float4 b) { return make_float4 (a.x+b.x, a.y+b.y, a.z+b.z, a.w+b.w); } __device__ __forceinline__ float4 cuSsub4 (const float4 a, const float4 b) { return make_float4 (a.x-b.x, a.y-b.y, a.z-b.z, a.w-b.w); } __device__ __forceinline__ float4 cuSmul14 (const float a, const float4 b) { return make_float4 (a*b.x, a*b.y, a*b.z, a*b.w); } __device__ __forceinline__ float4 cuSmad144 (const float a, const float4 b, const float4 c) { return make_float4 (a*b.x+c.x, a*b.y+c.y, a*b.z+c.z, a*b.w+c.w); } __device__ __forceinline__ float4 cuSmad414 (const float4 a, const float b, const float4 c) { return make_float4 (a.x*b+c.x, a.y*b+c.y, a.z*b+c.z, a.w*b+c.w); } __device__ __forceinline__ float4 cuSmad4 (const float4 a, const float4 b, const float4 c) { return make_float4 (a.x*b.x+c.x, a.y*b.y+c.y, a.z*b.z+c.z, a.w*b.w+c.w); } // ================================================================= #endif blas_dot2_v01a/src/Makefile000644 000765 000024 00000003323 13532136401 017011 0ustar00mukunokistaff000000 000000 # Makefile include ../make.inc CPP = gcc NVCC = $(CUDA_PATH)/bin/nvcc AR = ar LIB := ../lib/libmublas.a FLAGS := -O3 NVCCFLAGS := $(FLAGS) -Xcompiler -fPIC #--ptxas-options=-v #--ptxas-options=-v #--compiler-options='-finstrument-functions' -g all: blas ifeq ($(CC60),yes) NVCCFLAGS += -gencode arch=compute_60,code=sm_60 endif ifeq ($(CC61),yes) NVCCFLAGS += -gencode arch=compute_61,code=sm_61 endif ifeq ($(CC70),yes) NVCCFLAGS += -gencode arch=compute_70,code=sm_70 endif ifeq ($(CC6070),yes) NVCCFLAGS += -gencode arch=compute_60,code=sm_70 endif #ALLSRC = mublas.cpp ALLHDR = mublas_devel.h ifeq ($(DOT),yes) ALLSRC += mublas_dot.cu ALLHDR += mublas_dot_kernel.cu endif ifeq ($(GEMV),yes) ALLSRC += mublas_gemv.cu ALLHDR += mublas_gemv_n.incl ALLHDR += mublas_gemv_n_kernel.cu endif ifeq ($(GEMM),yes) ALLSRC += mublas_gemm.cu ALLHDR += mublas_gemm_nn_kernel.cu ALLHDR += mublas_dxgemm_nn_kernel.cu endif ifeq ($(CSRMV),yes) ALLSRC += mublas_csrmv.cu ALLHDR += mublas_csrmv_n_kernel.cu endif ALLOBJ = mublas.o ifeq ($(PREC_S),yes) ALLOBJ += $(ALLSRC:.cu=.s.o) ALLHDR += prec_s.h endif ifeq ($(PREC_D),yes) ALLOBJ += $(ALLSRC:.cu=.d.o) ALLHDR += prec_d.h endif ifeq ($(PREC_DX),yes) ALLOBJ += $(ALLSRC:.cu=.dx.o) ALLHDR += prec_dx.h cudotk.h endif ifeq ($(PREC_SX),yes) ALLOBJ += $(ALLSRC:.cu=.sx.o) ALLHDR += prec_sx.h endif $(ALLOBJ) : $(ALLHDR) blas: $(ALLOBJ) $(AR) rv $(LIB) $(ALLOBJ) %.s.o: %.cu $(NVCC) $(NVCCFLAGS) -o $@ -c $< -DPREC_S %.d.o: %.cu $(NVCC) $(NVCCFLAGS) -o $@ -c $< -DPREC_D %.sx.o: %.cu $(NVCC) $(NVCCFLAGS) -o $@ -c $< -DPREC_SX %.dx.o: %.cu $(NVCC) $(NVCCFLAGS) -o $@ -c $< -DPREC_DX mublas.o: mublas.cpp $(CPP) $(FLAGS) -o $@ -c $< $(CUDA_INC) -fPIC clean : $(RM) *.o $(RM) $(LIB) blas_dot2_v01a/src/mublas_gemm.cu000644 000765 000024 00000007056 13532476107 020213 0ustar00mukunokistaff000000 000000 #include "mublas_devel.h" #ifdef PREC_DX #include "mublas_dxgemm_nn_kernel.cu" #else #include "mublas_gemm_nn_kernel.cu" #endif __host__ int32_t MUBLAS_GEMM ( mublasHandle_t* mh, const char transA, const char transB, const size_t m, const size_t n, const size_t k, const TYPE0 *alpha, const TYPE0 *a, const size_t lda, const TYPE0 *b, const size_t ldb, const TYPE0 *beta, TYPE0 *c, const size_t ldc ) { void (*kernel) (const SIZE_T, const SIZE_T, const SIZE_T, const TYPE0, const TYPE0*, const SIZE_T, const TYPE0*, const SIZE_T, const TYPE0, TYPE0*, const SIZE_T); dim3 threads, grid; mublasRecipeDefault (mh); #if defined (PREC_DX) if (*alpha != ONE0 || *beta != ZERO0) { printf ("Non-supported operation: alpha!=1 (%f), beta!=0 (%f)\n", *alpha, *beta); return 0; } #endif mh->m = m; mh->n = n; mh->k = k; mh->N_one = sizeof (TYPE0); mh->N_T = 1; #if defined (PREC_DX) mh->N_T = 1; mh->TxStatic = 16; mh->TyStatic = 16; mh->func_getShmPerBlk = &getShmPerBlk_GEMM_NN_rb1x1; mh->func_getBlkPerGrd = &getBlkPerGrd_GEMM_NN_rb1x1; kernel = &MUBLAS_GEMM_NN_DEVICE_tb16x16_rb1x1_s1_maxwell; #elif PREC_SX mh->N_T = 2; mh->TxStatic = 8; mh->TyStatic = 8; mh->func_getShmPerBlk = &getShmPerBlk_GEMM_NN_rb8x8; mh->func_getBlkPerGrd = &getBlkPerGrd_GEMM_NN_rb8x8; kernel = &MUBLAS_GEMM_NN_DEVICE_tb8x8_rb8x8_v2_maxwell; #else if (VEC4) { if ( (((long)lda%(128/sizeof(TYPE0)))%16 == 0) && (m%64 == 0) && (((long)ldb%(128/sizeof(TYPE0)))%16 == 0) && (n%64 == 0) && (((long)ldc%(128/sizeof(TYPE0)))%16 == 0) && (k%64 == 0) ) { mh->N_T = 4; } else { mh->N_T = 2; } } else if (VEC2) { mh->N_T = 2; } // --------------------------------------------- uint32_t kernel_number = 999; if (transB == 'N' || transB == 'n') { if (transA == 'N' || transA == 'n') { // NN-kernel mh->BlkDim = 2; if (mh->m % 16 == 0 && mh->n % 16 == 0 && mh->k % 16 == 0) { if (mh->N_T == 4) { kernel_number = 140; mh->TxStatic = 8; mh->TyStatic = 8; mh->func_getShmPerBlk = &getShmPerBlk_GEMM_NN_rb8x8; mh->func_getBlkPerGrd = &getBlkPerGrd_GEMM_NN_rb8x8; kernel = &MUBLAS_GEMM_NN_DEVICE_tb8x8_rb8x8_v4_maxwell; } else if (mh->N_T == 2) { kernel_number = 120; mh->TxStatic = 8; mh->TyStatic = 8; mh->func_getShmPerBlk = &getShmPerBlk_GEMM_NN_rb8x8; mh->func_getBlkPerGrd = &getBlkPerGrd_GEMM_NN_rb8x8; kernel = &MUBLAS_GEMM_NN_DEVICE_tb8x8_rb8x8_v2_maxwell; } else { kernel_number = 110; mh->TxStatic = 16; mh->TyStatic = 16; mh->func_getShmPerBlk = &getShmPerBlk_GEMM_NN_rb1x1; mh->func_getBlkPerGrd = &getBlkPerGrd_GEMM_NN_rb1x1; kernel = &MUBLAS_GEMM_NN_DEVICE_tb16x16_rb1x1_s1_maxwell; } } else { kernel_number = 110; mh->TxStatic = 16; mh->TyStatic = 16; mh->func_getShmPerBlk = &getShmPerBlk_GEMM_NN_rb1x1; mh->func_getBlkPerGrd = &getBlkPerGrd_GEMM_NN_rb1x1; kernel = &MUBLAS_GEMM_NN_DEVICE_tb16x16_rb1x1_s1_maxwell; } } else { // TN-kernel } } else { if (transA == 'N' || transA == 'n') { // NT-kernel } else { // TT-kernel } } if (kernel_number == 999) { printf ("mublas error: not implemented"); return 0; } #endif mh->func_cache = cudaFuncCachePreferShared; cudaFuncSetCacheConfig (kernel, mh->func_cache); cudaFuncSetAttribute (kernel, cudaFuncAttributePreferredSharedMemoryCarveout, 100); cudaFuncGetAttributes (&mh->funcatb, kernel); mublas_optimizer (mh); threads = dim3 (mh->Tx, mh->Ty); grid = dim3 (mh->Bx, mh->By); kernel <<< grid, threads >>> (m, n, k, *alpha, a, lda, b, ldb, *beta, c, ldc); return 0; } blas_dot2_v01a/src/.nfs00000000002a10dd000003f7000644 000765 000024 00000030000 13531160667 020676 0ustar00mukunokistaff000000 000000 b0VIM 7.2a U*/mukunokiedna00.lab.hpcs.cs.tsukuba.ac.jp~mukunoki/mublas-1.4.3/mublas/mublas_dot_kernel.cuutf-8 U3210#"! Utpad9[QjQ810 i P I H G  ~ 6 4 3 n m F 4  K : 9    [ I ,    `ON4o]@# fG4 [63yvhUTF6 m_NMFDC1"###undef LOAD4_Y#undef LOAD2_Y#undef LOAD1_Y#undef RESTRICT_Y#undef LOAD4_X#undef LOAD2_X#undef LOAD1_X#undef RESTRICT_X}#endif work[bx] = sr; if (tx == 0) SHFL_ADD (sr, i); for (i = T_W/2; i > 0; i >>= 1) #pragma unroll sr = ss[tx]; } __syncthreads (); ss[tx] = ADD (ss[tx], ss[tx+i]); if (tx < i) for (i = NTX_DOT/2; i >= T_W; i >>= 1) { #pragma unroll // Reduction __syncthreads (); ss[tx] = sr; } tid += gridDim.x * blockDim.x * 2; sr = MAD (LOAD(x[tid+blockDim.x]), LOAD(y[tid+blockDim.x]), sr); while (tid + blockDim.x < n) { tid = blockDim.x * 2 * blockIdx.x + threadIdx.x; } tid += gridDim.x * blockDim.x * 2; sr = MAD (LOAD(x[tid]), LOAD(y[tid]), sr); while (tid < n) { tid = blockDim.x * 2 * blockIdx.x + threadIdx.x; sr = N_ZERO_Internal; // Multiply-add FPValueInternal sr; __shared__ FPValueInternal ss[NTX_DOT]; unsigned int tid; unsigned int bx = blockIdx.x; unsigned int tx = threadIdx.x; unsigned int i; const int32_t rowid = blockIdx.x * Tx_B + iTx; const int32_t iTx = threadIdx.x; const int32_t Tx_B = blockDim.x;#if VEC1) { TYPE0 *w const TYPE0 * RESTRICT_Y y, const TYPE0 * RESTRICT_X x, const int32_t n,__global__ void MUBLAS_DOT_DEVICE_s1 ( *********************************************** */ kernel=s1/* ***********************************************}#endif Yr2 = (TYPE2&) y[rowid]; Xr2 = (TYPE2&) x[rowid]; TYPE2 Xr2, Yr2; const int32_t rowid = blockIdx.x * Tx_B * N_T + iTx * N_T; const int32_t iTx = threadIdx.x; const int32_t Tx_B = blockDim.x; const int32_t N_T = 2;#if VEC2) { TYPE0 *w const TYPE0 * RESTRICT_Y y, const TYPE0 * RESTRICT_X x, const int32_t n,__global__ void MUBLAS_DOT_DEVICE_v2 ( *********************************************** */ kernel=v2/* ***********************************************}#endif Yr4 = (TYPE4&) y[rowid]; Xr4 = (TYPE4&) x[rowid]; TYPE4 Xr4, Yr4; const int32_t rowid = blockIdx.x * Tx_B * N_T + iTx * N_T; const int32_t iTx = threadIdx.x; const int32_t Tx_B = blockDim.x; const int32_t N_T = 4;#if VEC4) { TYPE0 *w const TYPE0 * RESTRICT_Y y, const TYPE0 * RESTRICT_X x, const int32_t n,__global__ void MUBLAS_DOT_DEVICE_v4 ( *********************************************** */ kernel=v4/* ***********************************************} mh->S_B = 0.;__host__ __inline__ void get_SB_DOT ( mublasHandle_t* mh) {} mh->B_D = (int32_t) ceil ((float)mh->n / (float)(mh->N_T * mh->Tx_B));__host__ __inline__ void get_BD_DOT ( mublasHandle_t* mh) { *********************************************** */ Functions for determining Tx_B /* ***********************************************#endif#define LOAD4_Y LOAD4___#define LOAD2_Y LOAD2___#define LOAD1_Y LOAD1___#define RESTRICT_Y#else#define LOAD4_Y LOAD4_NC#define LOAD2_Y LOAD2_NC#define LOAD1_Y LOAD1_NC#define RESTRICT_Y __restrict__#if USE_NC_Y_DOT#endif#define LOAD4_X LOAD4___#define LOAD2_X LOAD2___#define LOAD1_X LOAD1___#define RESTRICT_X#else#define LOAD4_X LOAD4_NC#define LOAD2_X LOAD2_NC#define LOAD1_X LOAD1_NC#define RESTRICT_X __restrict__#if USE_NC_X_DOT *********************************************** */ Macro/* *********************************************** *********************************************** */ DOT/* ***********************************************blas_dot2_v01a/src/cudotk.h000644 000765 000024 00000003343 13531175505 017024 0ustar00mukunokistaff000000 000000 #ifndef CUDOT2_H #define CUDOT2_H #include "mublas_devel.h" /* *********************************************** Error Free Translations *********************************************** */ __device__ __forceinline__ void cuTwoSum (double a, double b, double &s, double &e) { double v; s = __dadd_rn (a, b); v = __dsub_rn (s, a); e = __dadd_rn ( __dsub_rn(a, __dsub_rn (s, v)), __dsub_rn (b, v)); } __device__ __forceinline__ void cuQuickTwoSum (double a, double b, double &s, double &e) { s = __dadd_rn (a, b); e = __dsub_rn (b, __dsub_rn (s, a)); } __device__ __forceinline__ void cuTwoProdFMA (double a, double b, double &p, double &e) { p = __dmul_rn (a, b); e = __fma_rn (a, b, -p); } /* *********************************************** Dot2-Arithmetic *********************************************** */ /* [p,s] = TwoProduct(x(1),y(1)); for i=2:length(x) [h,r] = TwoProduct(x(i),y(i)); [p,q] = TwoSum(p,h); s = s + ( q + r ); end res = p + s; */ // DOT2 __device__ __forceinline__ double cuDot2 (const double *x, const double *y, int n) { int i; double h, p, q, s, r; cuTwoProdFMA (x[0], y[0], p, s); for (i = 1; i < n; i++) { cuTwoProdFMA (x[i], y[i], h, r); cuTwoSum (p, h, p, q); s = s + (q + r); } return p + s; } __device__ __forceinline__ void cuDot2i (const double a, const double b, double2 &c) { double h, r, q; cuTwoProdFMA (a, b, h, r); cuTwoSum (c.x, h, c.x, q); c.y = c.y + (q + r); } __device__ __forceinline__ void cuDot2i_212 (const double2 a, const double b, double2 &cx, double2 &cy) { double h, r, q; cuTwoProdFMA (a.x, b, h, r); cuTwoSum (cx.x, h, cx.x, q); cx.y = cx.y + (q + r); cuTwoProdFMA (a.y, b, h, r); cuTwoSum (cy.x, h, cy.x, q); cy.y = cy.y + (q + r); } #endif blas_dot2_v01a/src/mublas_dxgemm_nn_kernel.cu000644 000765 000024 00000004221 13532475251 022570 0ustar00mukunokistaff000000 000000 #include "mublas_devel.h" __host__ __inline__ void getBlkPerGrd_GEMM_NN_rb1x1 (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; const uint32_t Bm = mh->Tx; const uint32_t Bn = mh->Ty; mh->Bx = ceilingEx ((float)mh->m / (float)Bm, 1); mh->By = ceilingEx ((float)mh->n / (float)Bn, 1); } __host__ __inline__ void getShmPerBlk_GEMM_NN_rb1x1 (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; const uint32_t Bm = mh->Tx; const uint32_t Bn = mh->Ty; const uint32_t Bk = mh->Tx; const uint32_t ShmUse = Bm * Bk + Bk * Bn; mh->ShmPerBlk = ceilingEx ((float)(ShmUse * mh->N_one), mh->ShmUnit); } __global__ void MUBLAS_GEMM_NN_DEVICE_tb16x16_rb1x1_s1_maxwell ( const size_t m, const size_t n, const size_t k, const double alpha, const double * __restrict__ Ag, const size_t lda, const double * __restrict__ Bg, const size_t ldb, const double beta, double *Cg, const size_t ldc ) { int32_t jk, ki; const int32_t iBx = blockIdx.x; const int32_t iBy = blockIdx.y; const int32_t iTx = threadIdx.x; const int32_t iTy = threadIdx.y; const int32_t addrx = iBx*16+iTx; const int32_t addry = iBy*16+iTy; __shared__ double As1[16][16+1]; __shared__ double Bs1[16][16+1]; register double Ar1, Br1, Cr1; register TYPE1 Tr1; double * addrCg = &Cg[addry*ldc + addrx]; Tr1 = ZERO1; jk = 0; if (k > 16){ for (jk = 0; jk < k-16; jk += 16) { LOAD1_NC (As1[iTy][iTx], &Ag[(jk+iTy)*lda + min(m-1,addrx)]); LOAD1_NC (Br1, &Bg[min(n-1,addry)*ldb + (iTx+jk)]); Bs1[iTx][iTy] = Br1; __syncthreads (); #pragma unroll for (ki = 0; ki < 16; ki++) { Ar1 = As1[ki][iTx]; Br1 = Bs1[ki][iTy]; cuDot2i (Ar1, Br1, Tr1); } __syncthreads (); } } { LOAD1_NC (As1[iTy][iTx], &Ag[min(k-1,jk+iTy)*lda + min(m-1,addrx)]); LOAD1_NC (Br1, &Bg[min(n-1,addry)*ldb + min(k-1,iTx+jk)]); Bs1[iTx][iTy] = Br1; __syncthreads (); #pragma unroll for (ki = 0; ki+jk < k; ki++) { Ar1 = As1[ki][iTx]; Br1 = Bs1[ki][iTy]; cuDot2i (Ar1, Br1, Tr1); } __syncthreads (); } if (addrx < m && addry < n) { LOAD1___ (Cr1, addrCg); Cr1 = MAD1 (LOAD0(alpha), (Tr1.x+Tr1.y), MUL1 (LOAD0(beta), Cr1)); STORE1___ (addrCg, Cr1); } } blas_dot2_v01a/src/prec_dx.h000644 000765 000024 00000007506 13532136464 017166 0ustar00mukunokistaff000000 000000 #ifndef PREC_DX_H #define PREC_DX_H #include "cudotk.h" #ifdef PREC_DX // host #define MUBLAS_CSRMV mublasDXcsrmv #define MUBLAS_MATCONV mublasDtoDXmatconv #define MUBLAS_GEMM mublasDXgemm #define MUBLAS_GEMV mublasDXgemv #define MUBLAS_DOT mublasDXdot #define CUBLAS_GEMM cublasDgemm #define TYPE0 double #define ZERO0 0. #define ONE0 1. #define LOAD0(A) (A) // vec1 #define VEC1 1 #define TYPE1 double2 #define ZERO1 make_double2(0.,0.) #define ONE1 ONE0 #define ADD1(A,B) ((A)+(B)) #define MUL1(A,B) ((A)*(B)) #define MAD1(A,B,C) (((A)*(B))+(C)) #define LOAD1___ ld_global_f64 #define LOAD1_NC ld_global_nc_f64 #define STORE1___ st_global_f64 // vec2 #define VEC2 0 // vec4 #define VEC4 0 #endif // === Shuffle ===================================================== __device__ __forceinline__ void shuffleAdd (double &val, const int n) { #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 300) val += __hiloint2double( __shfl_xor_sync(0xFFFFFFFF, __double2hiint(val), n, WrpSize), __shfl_xor_sync(0xFFFFFFFF, __double2loint(val), n, WrpSize)); #endif } __device__ __forceinline__ double shuffleGet (double &val, const int n) { #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 300) return __hiloint2double( __shfl_xor_sync(0xFFFFFFFF, __double2hiint(val), n, WrpSize), __shfl_xor_sync(0xFFFFFFFF, __double2loint(val), n, WrpSize)); #endif } // ================================================================= // === Load ======================================================== __device__ __forceinline__ void ld_global_f64 (double ®, const double *addr) { #if USE_INLINE_ASM asm ("ld.global.f64 %0, [%1];": "=d"(reg): "l"(addr)); #else reg = *addr; #endif } __device__ __forceinline__ void ld_global_nc_f64 (double ®, const double *addr) { #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.f64 %0, [%1];": "=d"(reg): "l"(addr)); #else asm ("ld.global.f64 %0, [%1];": "=d"(reg): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) reg = __ldg(addr); #else reg = *addr; #endif #endif } __device__ __forceinline__ void ld_global_v2_f64 (double2 ®, const double *addr) { #if USE_INLINE_ASM asm ("ld.global.v2.f64 {%0,%1}, [%2];": "=d"(reg.x), "=d"(reg.y): "l"(addr)); #else reg = (double2&)*addr; #endif } __device__ __forceinline__ void ld_global_nc_v2_f64 (double2 ®, const double *addr) { #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.v2.f64 {%0,%1}, [%2];": "=d"(reg.x), "=d"(reg.y): "l"(addr)); #else asm ("ld.global.v2.f64 {%0,%1}, [%2];": "=d"(reg.x), "=d"(reg.y): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) reg = __ldg((double2*)addr); #else reg = (double2&)*addr; #endif #endif } // ================================================================= // === Store ======================================================= __device__ __forceinline__ void st_global_f64 (double *addr, const double reg) { #if USE_INLINE_ASM asm ("st.global.f64 [%0], %1;":: "l"(addr), "d"(reg)); #else *addr = reg; #endif } __device__ __forceinline__ void st_global_v2_f64 (double *addr, const double2 reg) { #if USE_INLINE_ASM asm ("st.global.v2.f64 [%0], {%1,%2};":: "l"(addr), "d"(reg.x), "d"(reg.y)); #else (double2&)*addr = reg; #endif } // ================================================================= // ================================================================= __device__ __forceinline__ double2 cuDadd2 (const double2 a, const double2 b) { return make_double2 (a.x+b.x, a.y+b.y); } __device__ __forceinline__ double2 cuDmul12 (const double a, const double2 b) { return make_double2 (a*b.x, a*b.y); } __device__ __forceinline__ double2 cuDmad122 (const double a, const double2 b, const double2 c) { return make_double2 (a*b.x+c.x, a*b.y+c.y); } #endif blas_dot2_v01a/src/mublas_dot_kernel.cu000644 000765 000024 00000005373 13532134130 021377 0ustar00mukunokistaff000000 000000 /* *********************************************** DOT *********************************************** */ __global__ void empty_kernel ( ) { // printf ("ok\n"); } /* *********************************************** kernel=s1 *********************************************** */ __global__ void MUBLAS_SUM_DEVICE_s1 ( SIZE_T n, TYPE1 *w ) { const int32_t Tx = NTX_SUM;//blockDim.x; const int32_t iTx = threadIdx.x; int32_t i, idx; TYPE1 Wr1, Tr1; __shared__ TYPE1 Ts1[NTX_SUM]; Tr1 = ZERO1; for (idx = iTx; idx < n; idx += Tx) { Wr1 = w[idx]; #ifdef PREC_DX double q; cuTwoSum (Tr1.x, Wr1.x, Tr1.x, q); Tr1.y = Tr1.y + (q + Wr1.y); #else Tr1 = ADD1 (Wr1, Tr1); #endif } Ts1[iTx] = Tr1; __syncthreads (); #pragma unroll for (i = Tx/2; i >= WrpSize; i >>= 1) { if (iTx < i) { #ifdef PREC_DX double q; cuTwoSum (Ts1[iTx].x, Ts1[iTx+i].x, Ts1[iTx].x, q); Ts1[iTx].y = Ts1[iTx].y + (q + Ts1[iTx+i].y); #else Ts1[iTx] = ADD1 (Ts1[iTx], Ts1[iTx+i]); #endif } __syncthreads (); } Tr1 = Ts1[iTx]; #pragma unroll for (i = WrpSize/2; i > 0; i >>= 1) { #ifdef PREC_DX double q; cuTwoSum (Tr1.x, shuffleGet (Tr1.x, i), Tr1.x, q); Tr1.y = Tr1.y + (q + shuffleGet (Tr1.y, i)); #else shuffleAdd (Tr1, i); #endif } if (iTx == 0) { #ifdef PREC_DX STORE1___ (&w[0].x, (Tr1.x+Tr1.y)); #elif PREC_SX (float&)w[0] = (float)Tr1; #else w[0] = Tr1; #endif } } __global__ void MUBLAS_DOT_DEVICE_s1 ( const SIZE_T n, const TYPE0 * __restrict__ x, const TYPE0 * __restrict__ y, TYPE1 *w ) { #if VEC1 const SIZE_T Tx = NTX_DOT;//blockDim.x; const SIZE_T Bx = gridDim.x; const SIZE_T iTx = threadIdx.x; const SIZE_T iBx = blockIdx.x; SIZE_T i, idx; #ifdef PREC_DX TYPE0 Xr1, Yr1; #else TYPE1 Xr1, Yr1; #endif TYPE1 Tr1; __shared__ TYPE1 Ts1[NTX_DOT]; // Multiply-add Tr1 = ZERO1; // for (idx = iBx*ceilf((float)n/Bx)+iTx; idx < min ((iBx+1)*ceilf((float)n/Bx),n); idx += Tx) { for (idx = iBx * Tx + iTx; idx < n; idx += Bx * Tx) { LOAD1_NC (Xr1, &x[idx]); LOAD1_NC (Yr1, &y[idx]); #ifdef PREC_DX cuDot2i (Xr1, Yr1, Tr1); #else Tr1 = MAD1 (Xr1, Yr1, Tr1); #endif } Ts1[iTx] = Tr1; __syncthreads (); // Reduction #pragma unroll for (i = Tx/2; i >= WrpSize; i >>= 1) { if (iTx < i) { #ifdef PREC_DX double q; cuTwoSum (Ts1[iTx].x, Ts1[iTx+i].x, Ts1[iTx].x, q); Ts1[iTx].y = Ts1[iTx].y + (q + Ts1[iTx+i].y); #else Ts1[iTx] = ADD1 (Ts1[iTx], Ts1[iTx+i]); #endif } __syncthreads (); } Tr1 = Ts1[iTx]; #pragma unroll for (i = WrpSize/2; i > 0; i >>= 1) { #ifdef PREC_DX double q; cuTwoSum (Tr1.x, shuffleGet (Tr1.x, i), Tr1.x, q); Tr1.y = Tr1.y + (q + shuffleGet (Tr1.y, i)); #else shuffleAdd (Tr1, i); #endif } if (iTx == 0) w[iBx] = Tr1; #endif } blas_dot2_v01a/src/mublas_dot.cu000644 000765 000024 00000002136 13532474770 020052 0ustar00mukunokistaff000000 000000 //#define SDOT2 #define NBX_DOT 1024 #define NTX_DOT 128 #define NTX_SUM 128 #include "mublas_devel.h" #if defined (SDOT2) && (PREC_SX) #undef TYPE1 #undef ZERO1 #define TYPE1 float2 #define ZERO1 make_float2(0.,0.) #include "mublas_dot_kernel_sdot2.cu" #else #include "mublas_dot_kernel.cu" #endif __host__ int32_t MUBLAS_DOT ( mublasHandle_t* mh, const size_t n, const TYPE0 *x, const size_t incx, const TYPE0 *y, const size_t incy, TYPE0 *result ) { #ifndef SDOT2 if (n == 0){ empty_kernel <<< dim3(1), dim3(1) >>> (); return 0; } #endif mublasRecipeDefault (mh); uint32_t Tx = NTX_DOT; uint32_t Bx = min (NBX_DOT, ceil((float)n/Tx)); dim3 threads = dim3 (Tx); dim3 grid = dim3 (Bx); TYPE1 *d_result = (TYPE1*)mh->work_addr; MUBLAS_DOT_DEVICE_s1 <<< grid, threads >>> (n, x, y, d_result); threads = dim3 (NTX_SUM); grid = dim3 (1); MUBLAS_SUM_DEVICE_s1 <<< grid, threads >>> (Bx, d_result); if (!mh->pmode) cudaMemcpy (result, (TYPE0*)d_result, sizeof(TYPE0), cudaMemcpyDeviceToHost); else cudaMemcpy (result, (TYPE0*)d_result, sizeof(TYPE0), cudaMemcpyDeviceToDevice); return 0; } blas_dot2_v01a/src/mublas_gemv_n_kernel.cu000644 000765 000024 00000035530 13532136366 022077 0ustar00mukunokistaff000000 000000 /* *********************************************** GEMV-N for CUDA *********************************************** */ #define USE_NC_A_GEMV_N 1 #define USE_NC_X_GEMV_N 0 /* *********************************************** Macro *********************************************** */ #if USE_NC_A_GEMV_N #define RESTRICT_A __restrict__ #define LOAD1_A LOAD1_NC #define LOAD2_A LOAD2_NC #define LOAD4_A LOAD4_NC #else #define RESTRICT_A #define LOAD1_A LOAD1___ #define LOAD2_A LOAD2___ #define LOAD4_A LOAD4___ #endif #if USE_NC_X_GEMV_N #define RESTRICT_X __restrict__ #define LOAD1_X LOAD1_NC #define LOAD2_X LOAD2_NC #define LOAD4_X LOAD4_NC #else #define RESTRICT_X #define LOAD1_X LOAD1___ #define LOAD2_X LOAD2___ #define LOAD4_X LOAD4___ #endif #define LOAD1_Y LOAD1___ #define LOAD2_Y LOAD2___ #define LOAD4_Y LOAD4___ #define STORE1_Y STORE1___ #define STORE2_Y STORE2___ #define STORE4_Y STORE4___ /* *********************************************** Functions for determining Tx and Ty *********************************************** */ __host__ __inline__ void getBlkPerGrd_GEMV_N (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; mh->Bx = ceilingEx ((float)mh->m / (float)(mh->N_T * mh->Tx), 1); mh->By = 1; mh->Bz = 1; } __host__ __inline__ void getShmPerBlk_GEMV_N (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; #if defined (PREC_DX) || defined (PREC_SX) mh->ShmPerBlk = ceilingEx ((float)(mh->Tx * mh->Ty * mh->N_T * mh->N_one * 2), mh->ShmUnit); #else mh->ShmPerBlk = ceilingEx ((float)(mh->Tx * mh->Ty * mh->N_T * mh->N_one), mh->ShmUnit); #endif } __host__ __inline__ size_t getTxSuf_GEMV_N (mublasHandle_t* mh) { return (size_t)ceilingEx ((float)mh->m / (float)mh->N_T / (float)mh->devprop.multiProcessorCount, mh->TxStep); } /* *********************************************** kernel=s1, trans=N *********************************************** */ __global__ void MUBLAS_GEMV_N_DEVICE_s1 ( const SIZE_T m, const SIZE_T n, const TYPE0 alpha, const TYPE0 * RESTRICT_A Ag, const SIZE_T lda, const TYPE0 * RESTRICT_X Xg, const TYPE0 beta, TYPE0 *Yg ) { #if VEC1 const SIZE_T Tx = blockDim.x; const SIZE_T Ty = blockDim.y; const SIZE_T Th = Tx * Ty; const SIZE_T iTx = threadIdx.x; const SIZE_T iTy = threadIdx.y; const SIZE_T iTh = iTy * Tx + iTx; const SIZE_T rowid = (blockIdx.x * Tx + iTx); SIZE_T i, j, k; extern __shared__ TYPE1 Xs1[]; #ifdef PREC_DX TYPE0 Ar1, Xr1, Yr1; #else TYPE1 Ar1, Xr1, Yr1; #endif TYPE1 Tr1; Tr1 = ZERO1; // main for (i = 0; i < n/Th; i++) { k = i*Th; LOAD1_X (Xr1, &Xg[k + iTh]); #ifdef PREC_DX Xs1[iTh].x = Xr1; #else Xs1[iTh] = Xr1; #endif __syncthreads (); if (rowid < m) { for (j = iTy; j < Th; j+= Ty) { LOAD1_A (Ar1, &Ag[(j+k) * lda + rowid]); #ifdef PREC_DX cuDot2i (Xs1[j].x, Ar1, Tr1); #else Tr1 = MAD1 (Xs1[j], Ar1, Tr1); #endif } } __syncthreads (); } // last one block k = i*Th; if (k + iTh < n) { LOAD1_X (Xr1, &Xg[k + iTh]); #ifdef PREC_DX Xs1[iTh].x = Xr1; #else Xs1[iTh] = Xr1; #endif } __syncthreads (); if (rowid < m) { for (j = k + iTy; j < n; j += Ty) { if (j < n) { LOAD1_A (Ar1, &Ag[j * lda + rowid]); #ifdef PREC_DX cuDot2i (Xs1[j-k].x, Ar1, Tr1); #else Tr1 = MAD1 (Xs1[j-k], Ar1, Tr1); #endif } } } __syncthreads (); // reduction Xs1[iTh] = Tr1; __syncthreads (); if (iTy == 0) { for (i = 1; i < Ty; i++) { #ifdef PREC_DX double q; cuTwoSum (Tr1.x, Xs1[Tx * i + iTx].x, Tr1.x, q); Tr1.y = Tr1.y + (q + Xs1[Tx * i + iTx].y); #else Tr1 = ADD1 (Tr1, Xs1[Tx * i + iTx]); #endif } if (rowid < m) { if (alpha == ONE0 && beta == ZERO0) { #ifdef PREC_DX STORE1_Y (&Yg[rowid], Tr1.x+Tr1.y); #else STORE1_Y (&Yg[rowid], Tr1); #endif } else { LOAD1_Y (Yr1, &Yg[rowid]); #ifdef PREC_DX Yr1 = MAD1 (LOAD0(alpha), (Tr1.x+Tr1.y), MUL1 (LOAD0(beta), Yr1)); #else Yr1 = MAD1 (LOAD0(alpha), Tr1, MUL1 (LOAD0(beta), Yr1)); #endif STORE1_Y (&Yg[rowid], Yr1); } } } #endif } #if !defined (PREC_DX) /* *********************************************** kernel=v2, trans=N *********************************************** */ __global__ void MUBLAS_GEMV_N_DEVICE_v2 ( const SIZE_T m, const SIZE_T n, const TYPE0 alpha, const TYPE0 * RESTRICT_A Ag, const SIZE_T lda, const TYPE0 * RESTRICT_X Xg, const TYPE0 beta, TYPE0 *Yg ) { #if VEC2 const SIZE_T N_T = 2; const SIZE_T Tx = blockDim.x; const SIZE_T Ty = blockDim.y; const SIZE_T Th = Tx * Ty; const SIZE_T iTx = threadIdx.x; const SIZE_T iTy = threadIdx.y; const SIZE_T iTh = iTy * Tx + iTx; const SIZE_T rowid = (blockIdx.x * Tx + iTx) * N_T; SIZE_T i, j, k; extern __shared__ TYPE2 Xs2[]; TYPE2 Ar2, Xr2, Yr2, Tr2; TYPE1 Xr1, Yr1; Tr2 = ZERO2; // main for (i = 0; i < n/(Th*N_T); i++) { k = i*Th*N_T; LOAD2_X (Xr2, &Xg[k + iTh * N_T]); Xs2[iTh] = Xr2; __syncthreads (); if (rowid < m) { for (j = iTy*N_T; j < Th*N_T; j+= Ty*N_T) { LOAD2_A (Ar2, &Ag[(j+k+0) * lda + rowid]); Tr2 = MAD122 ((TYPE1&)Xs2[j/N_T].x, Ar2, Tr2); LOAD2_A (Ar2, &Ag[(j+k+1) * lda + rowid]); Tr2 = MAD122 ((TYPE1&)Xs2[j/N_T].y, Ar2, Tr2); } } __syncthreads (); } // last one block k = i*Th*N_T; if (n % N_T == 0) { if (k + iTh * N_T + 0 < n) { LOAD2_X (Xr2, &Xg[k + iTh * N_T]); Xs2[iTh] = Xr2; } } else { if (k + iTh * N_T + 0 < n) { LOAD1_X (Xr1, &Xg[k + iTh * N_T + 0]); (TYPE1&)Xs2[iTh].x = Xr1; } if (k + iTh * N_T + 1 < n) { LOAD1_X (Xr1, &Xg[k + iTh * N_T + 1]); (TYPE1&)Xs2[iTh].y = Xr1; } } __syncthreads (); if (rowid < m) { for (j = k + iTy * N_T; j < n; j += Ty*N_T) { if (j + 0 < n) { LOAD2_A (Ar2, &Ag[(j+0) * lda + rowid]); Tr2 = MAD122 ((TYPE1&)Xs2[(j-k)/N_T].x, Ar2, Tr2); } if (j + 1 < n) { LOAD2_A (Ar2, &Ag[(j+1) * lda + rowid]); Tr2 = MAD122 ((TYPE1&)Xs2[(j-k)/N_T].y, Ar2, Tr2); } } } __syncthreads (); // reduction Xs2[iTh] = Tr2; __syncthreads (); if (iTy == 0) { for (i = 1; i < Ty; i++) Tr2 = ADD2 (Tr2, Xs2[Tx * i + iTx]); if (alpha == ONE0 && beta == ZERO0) { if (m % N_T == 0) { if (rowid < m) STORE2_Y (&Yg[rowid ], Tr2); } else { if (rowid+0 < m) STORE1_Y (&Yg[rowid ], Tr2.x); if (rowid+1 < m) STORE1_Y (&Yg[rowid+1], Tr2.y); } } else { if (m % N_T == 0) { if (rowid < m) { LOAD2_Y (Yr2, &Yg[rowid]); Yr2 = MAD122 (LOAD0(alpha), Tr2, MUL12 (LOAD0(beta), Yr2)); STORE2_Y (&Yg[rowid], Yr2); } } else { if (rowid+0 < m) { LOAD1_Y (Yr1, &Yg[rowid+0]); Yr1 = MAD1 (LOAD0(alpha), (TYPE1&)Tr2.x, MUL1 (LOAD0(beta), Yr1)); STORE1_Y (&Yg[rowid], Yr1); } if (rowid+1 < m) { LOAD1_Y (Yr1, &Yg[rowid+1]); Yr1 = MAD1 (LOAD0(alpha), (TYPE1&)Tr2.y, MUL1 (LOAD0(beta), Yr1)); STORE1_Y (&Yg[rowid+1], Yr1); } } } } #endif } #if !defined (PREC_SX) /* *********************************************** kernel=v4, trans=N *********************************************** */ __global__ void MUBLAS_GEMV_N_DEVICE_v4 ( const SIZE_T m, const SIZE_T n, const TYPE0 alpha, const TYPE0 * RESTRICT_A Ag, const SIZE_T lda, const TYPE0 * RESTRICT_X Xg, const TYPE0 beta, TYPE0 *Yg ) { #if VEC4 const SIZE_T N_T = 4; const SIZE_T Tx = blockDim.x; const SIZE_T Ty = blockDim.y; const SIZE_T Th = Tx * Ty; const SIZE_T iTx = threadIdx.x; const SIZE_T iTy = threadIdx.y; const SIZE_T iTh = iTy * Tx + iTx; const SIZE_T rowid = (blockIdx.x * Tx + iTx) * N_T; SIZE_T i, j, k; extern __shared__ TYPE4 Xs4[]; TYPE4 Ar4, Xr4, Yr4, Tr4; TYPE1 Xr1, Yr1; Tr4 = ZERO4; // main for (i = 0; i < n/(Th*N_T); i++) { k = i*Th*N_T; LOAD4_X (Xr4, &Xg[k + iTh * N_T]); Xs4[iTh] = Xr4; __syncthreads (); if (rowid < m) { for (j = iTy*N_T; j < Th*N_T; j+= Ty*N_T) { LOAD4_A (Ar4, &Ag[(j+k+0) * lda + rowid]); Tr4 = MAD144 (Xs4[j/N_T].x, Ar4, Tr4); LOAD4_A (Ar4, &Ag[(j+k+1) * lda + rowid]); Tr4 = MAD144 (Xs4[j/N_T].y, Ar4, Tr4); LOAD4_A (Ar4, &Ag[(j+k+2) * lda + rowid]); Tr4 = MAD144 (Xs4[j/N_T].z, Ar4, Tr4); LOAD4_A (Ar4, &Ag[(j+k+3) * lda + rowid]); Tr4 = MAD144 (Xs4[j/N_T].w, Ar4, Tr4); } } __syncthreads (); } // last one block k = i*Th*N_T; if (n % N_T == 0) { if (k + iTh * N_T < n) { LOAD4_X (Xr4, &Xg[k + iTh * N_T]); Xs4[iTh] = Xr4; } } else { if (k + iTh * N_T + 0 < n) { LOAD1_X (Xr1, &Xg[k + iTh * N_T + 0]); Xs4[iTh].x = Xr1; } if (k + iTh * N_T + 1 < n) { LOAD1_X (Xr1, &Xg[k + iTh * N_T + 1]); Xs4[iTh].y = Xr1; } if (k + iTh * N_T + 2 < n) { LOAD1_X (Xr1, &Xg[k + iTh * N_T + 2]); Xs4[iTh].z = Xr1; } if (k + iTh * N_T + 3 < n) { LOAD1_X (Xr1, &Xg[k + iTh * N_T + 3]); Xs4[iTh].w = Xr1; } } __syncthreads (); if (rowid < m) { for (j = k + iTy * N_T; j < n; j += Ty*N_T) { if (j + 0 < n) { LOAD4_A (Ar4, &Ag[(j+0) * lda + rowid]); Tr4 = MAD144 (Xs4[(j-k)/N_T].x, Ar4, Tr4); } if (j + 1 < n) { LOAD4_A (Ar4, &Ag[(j+1) * lda + rowid]); Tr4 = MAD144 (Xs4[(j-k)/N_T].y, Ar4, Tr4); } if (j + 2 < n) { LOAD4_A (Ar4, &Ag[(j+2) * lda + rowid]); Tr4 = MAD144 (Xs4[(j-k)/N_T].z, Ar4, Tr4); } if (j + 3 < n) { LOAD4_A (Ar4, &Ag[(j+3) * lda + rowid]); Tr4 = MAD144 (Xs4[(j-k)/N_T].w, Ar4, Tr4); } } } __syncthreads (); // reduction Xs4[iTh] = Tr4; __syncthreads (); if (iTy == 0) { for (i = 1; i < Ty; i++) Tr4 = ADD4 (Tr4, Xs4[Tx * i + iTx]); if (alpha == ONE0 && beta == ZERO0) { if (m % N_T == 0) { if (rowid < m) STORE4_Y (&Yg[rowid], Tr4); } else { if (rowid+0 < m) STORE1_Y (&Yg[rowid+0], Tr4.x); if (rowid+1 < m) STORE1_Y (&Yg[rowid+1], Tr4.y); if (rowid+2 < m) STORE1_Y (&Yg[rowid+2], Tr4.z); if (rowid+3 < m) STORE1_Y (&Yg[rowid+3], Tr4.w); } } else { if (m % N_T == 0) { if (rowid < m) { LOAD4_Y (Yr4, &Yg[rowid]); Yr4 = MAD144 (LOAD0(alpha), Tr4, MUL14 (LOAD0(beta), Yr4)); STORE4_Y (&Yg[rowid], Yr4); } } else { if (rowid+0 < m) { LOAD1_Y (Yr1, &Yg[rowid+0]); Yr1 = MAD1 (LOAD0(alpha), Tr4.x, MUL1 (LOAD0(beta), Yr1)); STORE1_Y (&Yg[rowid+0], Yr1); } if (rowid+1 < m) { LOAD1_Y (Yr1, &Yg[rowid+1]); Yr1 = MAD1 (LOAD0(alpha), Tr4.y, MUL1 (LOAD0(beta), Yr1)); STORE1_Y (&Yg[rowid+1], Yr1); } if (rowid+2 < m) { LOAD1_Y (Yr1, &Yg[rowid+2]); Yr1 = MAD1 (LOAD0(alpha), Tr4.z, MUL1 (LOAD0(beta), Yr1)); STORE1_Y (&Yg[rowid+2], Yr1); } if (rowid+3 < m) { LOAD1_Y (Yr1, &Yg[rowid+3]); Yr1 = MAD1 (LOAD0(alpha), Tr4.w, MUL1 (LOAD0(beta), Yr1)); STORE1_Y (&Yg[rowid+3], Yr1); } } } } #endif } /* *********************************************** kernel=s2, trans=N *********************************************** */ __global__ void MUBLAS_GEMV_N_DEVICE_s2 ( const SIZE_T m, const SIZE_T n, const TYPE0 alpha, const TYPE0 * RESTRICT_A Ag, const SIZE_T lda, const TYPE0 * RESTRICT_X Xg, const TYPE0 beta, TYPE0 *Yg ) { const SIZE_T N_T = 2; const SIZE_T Tx = blockDim.x; const SIZE_T Ty = blockDim.y; const SIZE_T Th = Tx * Ty; const SIZE_T iTx = threadIdx.x; const SIZE_T iTy = threadIdx.y; const SIZE_T iTh = iTy * Tx + iTx; const SIZE_T rowid = (blockIdx.x * Tx + iTx) * N_T; SIZE_T i, j, k, l; extern __shared__ TYPE1 Xs1[]; TYPE1 Ar1, Xr1, Yr1, Tr1[2]; #pragma unroll for (l = 0; l < N_T; l++) Tr1[l] = ZERO1; // main for (i = 0; i < n/Th; i++) { k = i*Th; LOAD1_X (Xr1, &Xg[k + iTh]); Xs1[iTh] = Xr1; __syncthreads (); if (rowid < m) { for (j = iTy; j < Th; j+= Ty) { #pragma unroll for (l = 0; l < N_T; l++) { LOAD1_A (Ar1, &Ag[(j+k) * lda + rowid+l]); Tr1[l] = MAD1 (Xs1[j], Ar1, Tr1[l]); } } } __syncthreads (); } // last one block k = i*Th; if (k + iTh < n) { LOAD1_X (Xr1, &Xg[k + iTh]); Xs1[iTh] = Xr1; } __syncthreads (); if (rowid < m) { for (j = k + iTy; j < n; j += Ty) { #pragma unroll for (l = 0; l < N_T; l++) { LOAD1_A (Ar1, &Ag[j * lda + rowid+l]); Tr1[l] = MAD1 (Xs1[j-k], Ar1, Tr1[l]); } } } __syncthreads (); // reduction #pragma unroll for (l = 0; l < N_T; l++) Xs1[iTh*N_T+l] = Tr1[l]; __syncthreads (); if (iTy == 0) { for (i = 1; i < Ty; i++) { #pragma unroll for (l = 0; l < N_T; l++) Tr1[l] = ADD1 (Tr1[l], Xs1[(Tx * i + iTx)*N_T+l]); } if (alpha == ONE0 && beta == ZERO0) { #pragma unroll for (l = 0; l < N_T; l++) { if (rowid+l < m) STORE1_Y (&Yg[rowid+l], Tr1[l]); } } else { #pragma unroll for (l = 0; l < N_T; l++) { if (rowid+l < m) { LOAD1_Y (Yr1, &Yg[rowid+l]); Yr1 = MAD1 (LOAD0(alpha), Tr1[l], MUL1 (LOAD0(beta), Yr1)); STORE1_Y (&Yg[rowid+l], Yr1); } } } } } /* *********************************************** kernel=s4, trans=N *********************************************** */ __global__ void MUBLAS_GEMV_N_DEVICE_s4 ( const SIZE_T m, const SIZE_T n, const TYPE0 alpha, const TYPE0 * RESTRICT_A Ag, const SIZE_T lda, const TYPE0 * RESTRICT_X Xg, const TYPE0 beta, TYPE0 *Yg ) { const SIZE_T N_T = 4; const SIZE_T Tx = blockDim.x; const SIZE_T Ty = blockDim.y; const SIZE_T Th = Tx * Ty; const SIZE_T iTx = threadIdx.x; const SIZE_T iTy = threadIdx.y; const SIZE_T iTh = iTy * Tx + iTx; const SIZE_T rowid = (blockIdx.x * Tx + iTx) * N_T; SIZE_T i, j, k, l; extern __shared__ TYPE1 Xs1[]; TYPE1 Ar1, Xr1, Yr1, Tr1[4]; #pragma unroll for (l = 0; l < N_T; l++) Tr1[l] = ZERO1; // main for (i = 0; i < n/Th; i++) { k = i*Th; LOAD1_X (Xr1, &Xg[k + iTh]); Xs1[iTh] = Xr1; __syncthreads (); if (rowid < m) { for (j = iTy; j < Th; j+= Ty) { #pragma unroll for (l = 0; l < N_T; l++) { LOAD1_A (Ar1, &Ag[(j+k) * lda + rowid+l]); Tr1[l] = MAD1 (Xs1[j], Ar1, Tr1[l]); } } } __syncthreads (); } // last one block k = i*Th; if (k + iTh < n) { LOAD1_X (Xr1, &Xg[k + iTh]); Xs1[iTh] = Xr1; } __syncthreads (); if (rowid < m) { for (j = k + iTy; j < n; j += Ty) { #pragma unroll for (l = 0; l < N_T; l++) { LOAD1_A (Ar1, &Ag[j * lda + rowid+l]); Tr1[l] = MAD1 (Xs1[j-k], Ar1, Tr1[l]); } } } __syncthreads (); // reduction #pragma unroll for (l = 0; l < N_T; l++) Xs1[iTh*N_T+l] = Tr1[l]; __syncthreads (); if (iTy == 0) { for (i = 1; i < Ty; i++) { #pragma unroll for (l = 0; l < N_T; l++) Tr1[l] = ADD1 (Tr1[l], Xs1[(Tx * i + iTx)*N_T+l]); } if (alpha == ONE0 && beta == ZERO0) { #pragma unroll for (l = 0; l < N_T; l++) { if (rowid+l < m) STORE1_Y (&Yg[rowid+l], Tr1[l]); } } else { #pragma unroll for (l = 0; l < N_T; l++) { if (rowid+l < m) { LOAD1_Y (Yr1, &Yg[rowid+l]); Yr1 = MAD1 (LOAD0(alpha), Tr1[l], MUL1 (LOAD0(beta), Yr1)); STORE1_Y (&Yg[rowid+l], Yr1); } } } } } #endif #endif #undef RESTRICT_A #undef RESTRICT_X #undef LOAD1_A #undef LOAD2_A #undef LOAD4_A #undef LOAD1_X #undef LOAD2_X #undef LOAD4_X #undef LOAD1_Y #undef LOAD2_Y #undef LOAD4_Y #undef STORE1_Y #undef STORE2_Y #undef STORE4_Y blas_dot2_v01a/src/mublas.cpp000644 000765 000024 00000022122 13532136672 017350 0ustar00mukunokistaff000000 000000 #include "mublas_devel.h" /* *********************************************** Default Recipe *********************************************** */ void mublasRecipeDefault (mublasHandle_t *mh) { // -------------------------------------------------------- mh->WrpOcpSuf = 1.0;//14.0 * (float)mh->WrpGran / (float)mh->WrpPerMpPmax; mh->BlkOcpSuf = 1.0;// 0.0 / (float)mh->BlkPerMpPmax; mh->GrdOcpSuf = 1.0; mh->TyPerTxMax = 1.0; //1024=none // -------------------------------------------------------- mh->TxMin = 0; //0=auto:=TxStep mh->TxMax = 0; mh->TxStep = 0; //0=auto:128/sizeof(val) mh->ThMin = 0; //0=auto:ThMin=TxStep mh->ThMax = 0; //0=auto:maxThreadsPerBlock mh->ThStep = 0; //0=auto=TxStep // -------------------------------------------------------- } // compute shmem availability __host__ __inline__ void getShmSize (mublasHandle_t* mh) { size_t res; enum cudaFuncCache func_cache; cudaDeviceGetCacheConfig (&func_cache); const size_t preferS = 98304; const size_t preferL = 0; if (mh->devprop.major == 7) { switch (mh->func_cache) { case cudaFuncCachePreferNone: mh->ShmPerBlkMax = preferS; break; case cudaFuncCachePreferShared: mh->ShmPerBlkMax = preferS; break; case cudaFuncCachePreferL1: mh->ShmPerBlkMax = preferL; break; } } else { printf ("warning: shared-memory capacity may be incorrect.\n"); } } __host__ __inline__ size_t ThSizeCheck (mublasHandle_t *mh) { if (((mh->Tx * mh->Ty) % 32 == 0) && (mh->ShmPerBlkMax >= mh->ShmPerBlk)) return 1; return 0; } /* *********************************************** Occupancy Calculation *********************************************** */ __host__ __inline__ void getOccupancies (mublasHandle_t *mh) { const size_t RegPerWrp = ceilingEx ((float)(mh->funcatb.numRegs * WrpSize), mh->RegUnit); // Usage of registers per warp const size_t WrpPerBlk = ceil ((float)(mh->Tx * mh->Ty) / (float)WrpSize); // Warps per block const size_t BlkPerMpRmax = floor (min (floorEx ((float)mh->devprop.regsPerMultiprocessor / (float)RegPerWrp, mh->WrpGran), mh->WrpPerMpPmax) / (float)WrpPerBlk); const size_t BlkPerMpSmax = (mh->ShmPerBlk>0) ? floor ((float)mh->ShmPerBlkMax / (float)mh->ShmPerBlk) : mh->BlkPerMpPmax; mh->BlkPerMpMax = min (min (BlkPerMpRmax, BlkPerMpSmax), mh->BlkPerMpPmax); mh->WrpOcp = (float)(mh->BlkPerMpMax * WrpPerBlk) / (float)mh->WrpPerMpPmax; mh->BlkOcp = (float)(mh->BlkPerMpMax) / (float)mh->BlkPerMpPmax; mh->GrdOcp = (float)(mh->Bx * mh->By * mh->Bz) / (float)ceilingEx (mh->Bx * mh->By * mh->Bz, mh->BlkPerMpMax * mh->devprop.multiProcessorCount); } __host__ void determine_best_thread_block_size_2d (mublasHandle_t *mh) { size_t TxTmp, TyTmp, TxStart, TxStop, TxStep; float GrdOcpPrev = 0., BlkOcpPrev = 0., WrpOcpPrev = 0.; void (*getShmPerBlk)(void*); void (*getBlkPerGrd)(void*); getShmPerBlk = mh->func_getShmPerBlk; getBlkPerGrd = mh->func_getBlkPerGrd; TxTmp = mh->TxMax; TyTmp = ceil ((float)mh->ThMin / TxTmp); // --- Tx ------------------------------------------------ mh->Tx = mh->TxMax; while (mh->Tx >= mh->TxMin) { // --- Ty ----------------------------------------------- mh->Ty = min (max (1, floor ((float)mh->ThMax / (float)mh->Tx)), mh->Tx * mh->TyPerTxMax); while (mh->Ty >= ceil ((float)mh->ThMin / (float)mh->Tx)) { getShmPerBlk (mh); if (ThSizeCheck(mh)) { getBlkPerGrd (mh); getOccupancies (mh); if (mh->WrpOcp >= min(WrpOcpPrev,mh->WrpOcpSuf) && mh->BlkOcp >= min(BlkOcpPrev,mh->BlkOcpSuf) && mh->GrdOcp >= min(GrdOcpPrev,mh->GrdOcpSuf)) { GrdOcpPrev = mh->GrdOcp; WrpOcpPrev = mh->WrpOcp; BlkOcpPrev = mh->BlkOcp; TxTmp = mh->Tx; TyTmp = mh->Ty; } } mh->Ty -= 1; } mh->Tx -= mh->TxStep; } mh->Tx = TxTmp; mh->Ty = TyTmp; } __host__ void determine_best_thread_block_size_1d (mublasHandle_t *mh) { size_t TxTmp; float GrdOcpPrev = 0., BlkOcpPrev = 0., WrpOcpPrev = 0.; void (*getShmPerBlk)(void*); void (*getBlkPerGrd)(void*); getShmPerBlk = mh->func_getShmPerBlk; getBlkPerGrd = mh->func_getBlkPerGrd; TxTmp = mh->TxMax; mh->Ty = 1; // --- Tx ------------------------------------------------ mh->Tx = mh->TxMax; while (mh->Tx >= mh->TxMin) { getShmPerBlk (mh); if (ThSizeCheck(mh)) { getBlkPerGrd (mh); getOccupancies (mh); if (mh->WrpOcp >= min(WrpOcpPrev,mh->WrpOcpSuf) && mh->BlkOcp >= min(BlkOcpPrev,mh->BlkOcpSuf) && mh->GrdOcp >= min(GrdOcpPrev,mh->GrdOcpSuf)) { GrdOcpPrev = mh->GrdOcp; BlkOcpPrev = mh->BlkOcp; WrpOcpPrev = mh->WrpOcp; TxTmp = mh->Tx; } } mh->Tx -= mh->TxStep; } mh->Tx = TxTmp; mh->Ty = 1; } __host__ void determine_best_thread_block_size_nvidia (mublasHandle_t *mh) { cudaOccError err_t; cudaOccDeviceProp occdevprop = (cudaOccDeviceProp) mh->devprop; cudaOccFuncAttributes occfuncatb = mh->funcatb; cudaOccDeviceState occdevstat; occdevstat.cacheConfig = (cudaOccCacheConfig) mh->func_cache; void (*getShmPerBlk)(void*); getShmPerBlk = mh->func_getShmPerBlk; getShmPerBlk (mh); int minGridSize, blockSize; err_t = cudaOccMaxPotentialOccupancyBlockSize( &minGridSize, &blockSize, // out &occdevprop, &occfuncatb, &occdevstat, mh->ShmPerBlk); printf ("minGridSize = %d, blockSize = %d, err_t = %d\n", minGridSize, blockSize, err_t); } // phase 2: determining optimal thread-block size __host__ void mublas_optimizer (mublasHandle_t *mh) { void (*getShmPerBlk)(void*); void (*getBlkPerGrd)(void*); getShmPerBlk = mh->func_getShmPerBlk; getBlkPerGrd = mh->func_getBlkPerGrd; getShmSize(mh); // --- Initial Tx & Ty ------------------------------- // 1. TxStep (0=auto) if (mh->TxStep == 0) mh->TxStep = 128 / (mh->N_one * mh->N_T); // 128bytes/16bytes(vec)=8thread // 2. ThStep (0=auto) if (mh->ThStep == 0) mh->ThStep = mh->TxStep;//WrpSize; // 3. ThMin (0=auto) if (mh->ThMin == 0) mh->ThMin = mh->WrpGran * WrpSize; // 4. ThMax if (mh->ThMax == 0) mh->ThMax = mh->funcatb.maxThreadsPerBlock; // 5. TxMin if (mh->TxMin == 0) mh->TxMin = mh->TxStep; if (mh->BlkDim == 1) mh->TxMin = max (mh->TxMin, mh->ThMin); // 6. TxMax if (mh->TxMax == 0) mh->TxMax = mh->ThMax; // --------------------------------------------------- if (mh->TxStatic == 0) { if (mh->BlkDim == 2) determine_best_thread_block_size_2d (mh); else if (mh->BlkDim == 1) determine_best_thread_block_size_1d (mh); else printf ("mublas error: unsupported BlkDim\n"); } else { // Kernel is launched with specified Tx and Ty (static mode) mh->Tx = mh->TxStatic; mh->Ty = mh->TyStatic; if (mh->Tx * mh->Ty > mh->funcatb.maxThreadsPerBlock) { printf ("mublas error: too many resource requested\n"); printf ("debug info: mh->Tx = %d, mh->Ty = %d\n", mh->Tx, mh->Ty); exit (1); } } // determine_best_thread_block_size_nvidia (mh); // debug, cuda_occupancy.h getBlkPerGrd (mh); getShmPerBlk (mh); getOccupancies (mh); } /* *********************************************** mublas functions *********************************************** */ void mublasGetDevParams (mublasHandle_t *mh) { // default value (architecture dependent) switch (mh->cc) { case 600: mh->WrpPerMpPmax = 64; mh->BlkPerMpPmax = 32; mh->RegUnit = 256; mh->ShmUnit = 256; mh->WrpGran = 2; mh->Cores = 64; mh->DPCores = 32; break; case 610: mh->WrpPerMpPmax = 64; mh->BlkPerMpPmax = 32; mh->RegUnit = 256; mh->ShmUnit = 256; mh->WrpGran = 4; mh->Cores = 128; mh->DPCores = 4; break; case 620: mh->WrpPerMpPmax = 64; mh->BlkPerMpPmax = 32; mh->RegUnit = 256; mh->ShmUnit = 256; mh->WrpGran = 4; mh->Cores = 128; mh->DPCores = 4; break; case 700: mh->WrpPerMpPmax = 64; mh->BlkPerMpPmax = 32; mh->RegUnit = 256; mh->ShmUnit = 256; mh->WrpGran = 4; mh->Cores = 64; mh->DPCores = 32; break; default: // non-supported architecture printf ("error: non-supported architecture\n"); break; } } void mublasCreateSimple (mublasHandle_t *mh) { int32_t devid; cudaDeviceProp devprop; cudaGetDevice (&devid); cudaGetDeviceProperties (&devprop, devid); mh->devprop = devprop; mh->cc = devprop.major * 100 + devprop.minor * 10; mublasGetDevParams (mh); mh->WrpOcp = 0.; mh->BlkOcp = 0.; mh->GrdOcp = 0.; } void mublasCreate (mublasHandle_t *mh) { int32_t driverVersion = 0; int32_t runtimeVersion = 0; int32_t devid; cudaDriverGetVersion(&driverVersion); cudaRuntimeGetVersion(&runtimeVersion); // Device Properties cudaDeviceProp devprop; cudaGetDevice (&devid); cudaGetDeviceProperties (&devprop, devid); mh->devprop = devprop; mh->cc = devprop.major * 100 + devprop.minor * 10; mh->driverVersion = driverVersion; mh->runtimeVersion = runtimeVersion; // init mh->WrpOcp = 0.; mh->BlkOcp = 0.; mh->GrdOcp = 0.; mh->TxStatic = 0; mh->TyStatic = 0; mublasGetDevParams (mh); mh->pmode = 0; // 0=host, 1=device // work space allocation float *w, *w2; cudaMalloc ((void **) &w, sqrt((float)devprop.totalGlobalMem/(sizeof(double)*4))*sizeof(double)*4); cudaMalloc ((void **) &w2, sqrt((float)devprop.totalGlobalMem/(sizeof(double)*4))*sizeof(double)*4); mh->work_addr = w; mh->work_addr2 = w2; } void mublasDestroy (mublasHandle_t *mh) { cudaFree (mh->work_addr); cudaFree (mh->work_addr2); } blas_dot2_v01a/src/prec_d.h000644 000765 000024 00000014473 13532135634 016775 0ustar00mukunokistaff000000 000000 #ifndef PREC_D_H #define PREC_D_H #ifdef PREC_D #define MUBLAS_GEMM_NN_DEVICE_tb8x8_rb8x8_v4_maxwell mublasDgemm_NN_DEVICE_tb8x8_rb8x8_v4_maxwell #define MUBLAS_GEMM_NN_DEVICE_tb16x16_rb8x8_v2_maxwell mublasDgemm_NN_DEVICE_tb16x16_rb8x8_v2_maxwell #define MUBLAS_GEMM_NN_DEVICE_tb16x16_rb2x2_v2_maxwell mublasDgemm_NN_DEVICE_tb16x16_rb2x2_v2_maxwell #define MUBLAS_GEMM_NN_DEVICE_tb16x16_rb1x1_s1_maxwell mublasDgemm_NN_DEVICE_tb16x16_rb1x1_s1_maxwell #define MUBLAS_GEMM_TN_DEVICE_tb16x16_rb1x1_s1_maxwell mublasDgemm_TN_DEVICE_tb16x16_rb1x1_s1_maxwell #define MUBLAS_GEMM_TN_DEVICE_tb16x16_rb2x2_v2_maxwell mublasDgemm_TN_DEVICE_tb16x16_rb2x2_v2_maxwell #define MUBLAS_GEMM_NT_DEVICE_tb16x16_rb1x1_s1_maxwell mublasDgemm_NT_DEVICE_tb16x16_rb1x1_s1_maxwell #define MUBLAS_GEMM_NT_DEVICE_tb16x16_rb2x2_v2_maxwell mublasDgemm_NT_DEVICE_tb16x16_rb2x2_v2_maxwell #define MUBLAS_GEMM_TT_DEVICE_tb16x16_rb1x1_s1_maxwell mublasDgemm_TT_DEVICE_tb16x16_rb1x1_s1_maxwell #define MUBLAS_GEMM_TT_DEVICE_tb16x16_rb2x2_v2_maxwell mublasDgemm_TT_DEVICE_tb16x16_rb2x2_v2_maxwell // host #define MUBLAS_CSRMV mublasDcsrmv #define MUBLAS_GEMM mublasDgemm #define MUBLAS_GEMV mublasDgemv #define MUBLAS_DOT mublasDdot #define CUSPARSE_CSRMV cusparseDcsrmv #define CUBLAS_GEMM cublasDgemm #define CUBLAS_GEMV cublasDgemv #define CUBLAS_DOT cublasDdot #define TYPE0 double #define ZERO0 0. #define ONE0 1. #define LOAD0(A) (A) // vec1 #define VEC1 1 #define TYPE1 TYPE0 #define ZERO1 ZERO0 #define ONE1 ONE0 #define ADD1(A,B) ((A)+(B)) #define MUL1(A,B) ((A)*(B)) #define MAD1(A,B,C) (((A)*(B))+(C)) #define LOAD1___ ld_global_f64 #define LOAD1_NC ld_global_nc_f64 #define STORE1___ st_global_f64 // vec2 #define VEC2 1 #define TYPE2 double2 #define ZERO2 make_double2(0.,0.) #define ONE2 make_double2(1.,1.) #define ADD2 cuDadd2 #define MUL12 cuDmul12 #define MAD122 cuDmad122 #define MAD212 cuDmad212 #define MAD2 cuDmad2 #define LOAD2___ ld_global_v2_f64 #define LOAD2_NC ld_global_nc_v2_f64 #define STORE2___ st_global_v2_f64 // vec4 #define VEC4 0 #endif // === Shuffle ===================================================== __device__ __forceinline__ void shuffleAdd (double &val, const int n) { #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 300) val += __hiloint2double( __shfl_xor_sync(0xFFFFFFFF, __double2hiint(val), n, WrpSize), __shfl_xor_sync(0xFFFFFFFF, __double2loint(val), n, WrpSize)); #endif } // ================================================================= // === Load ======================================================== __device__ __forceinline__ void ld_global_v2_f64 (double2 ®, const double *addr) { #if USE_INLINE_ASM asm ("ld.global.v2.f64 {%0,%1}, [%2];": "=d"(reg.x), "=d"(reg.y): "l"(addr)); #else reg = (double2&)*addr; #endif } __device__ __forceinline__ void ld_global_f64 (double ®, const double *addr) { #if USE_INLINE_ASM asm ("ld.global.f64 %0, [%1];": "=d"(reg): "l"(addr)); #else reg = *addr; #endif } __device__ __forceinline__ void ld_global_nc_v2_f64 (double2 ®, const double *addr) { #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.v2.f64 {%0,%1}, [%2];": "=d"(reg.x), "=d"(reg.y): "l"(addr)); #else asm ("ld.global.v2.f64 {%0,%1}, [%2];": "=d"(reg.x), "=d"(reg.y): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) reg = __ldg((double2*)addr); #else reg = (double2&)*addr; #endif #endif } __device__ __forceinline__ void ld_global_nc_f64 (double ®, const double *addr) { #if USE_INLINE_ASM #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) asm ("ld.global.nc.f64 %0, [%1];": "=d"(reg): "l"(addr)); #else asm ("ld.global.f64 %0, [%1];": "=d"(reg): "l"(addr)); #endif #else #if defined (__CUDA_ARCH__) && (__CUDA_ARCH__ >= 320) reg = __ldg(addr); #else reg = *addr; #endif #endif } // ================================================================= // === Store ======================================================= __device__ __forceinline__ void st_global_v2_f64 (double *addr, const double2 reg) { #if USE_INLINE_ASM asm ("st.global.v2.f64 [%0], {%1,%2};":: "l"(addr), "d"(reg.x), "d"(reg.y)); #else (double2&)*addr = reg; #endif } __device__ __forceinline__ void st_global_f64 (double *addr, const double reg) { #if USE_INLINE_ASM asm ("st.global.f64 [%0], %1;":: "l"(addr), "d"(reg)); #else *addr = reg; #endif } // ================================================================= // === Vector ====================================================== __device__ __forceinline__ double2 cuDadd2 (const double2 a, const double2 b) { return make_double2 (a.x+b.x, a.y+b.y); } __device__ __forceinline__ double2 cuDmul12 (const double a, const double2 b) { return make_double2 (a*b.x, a*b.y); } __device__ __forceinline__ double2 cuDmad2 (const double2 a, const double2 b, const double2 c) { return make_double2 (a.x*b.x+c.x, a.y*b.y+c.y); } __device__ __forceinline__ double2 cuDmad122 (const double a, const double2 b, const double2 c) { return make_double2 (a*b.x+c.x, a*b.y+c.y); } __device__ __forceinline__ double2 cuDmad212 (const double2 a, const double b, const double2 c) { return make_double2 (a.x*b+c.x, a.y*b+c.y); } // ================================================================= // === Texture ===================================================== texture tex_mat_a; texture tex_mat_b; static __forceinline__ __device__ double tex_a(const int& i) { int2 v = tex1Dfetch (tex_mat_a, i); return __hiloint2double (v.y, v.x); } static __forceinline__ __device__ double tex_b(const int& i) { int2 v = tex1Dfetch (tex_mat_b, i); return __hiloint2double (v.y, v.x); } texture tex_mat_a_v2; texture tex_mat_b_v2; static __forceinline__ __device__ double2 tex_a_v2(const int& i) { register int4 v = tex1Dfetch (tex_mat_a_v2, i); return make_double2(__hiloint2double (v.y, v.x), __hiloint2double (v.w, v.z)); } static __forceinline__ __device__ double2 tex_b_v2(const int& i) { register int4 v = tex1Dfetch (tex_mat_b_v2, i); return make_double2(__hiloint2double (v.y, v.x), __hiloint2double (v.w, v.z)); } // ================================================================= #endif blas_dot2_v01a/src/mublas_gemv.cu000644 000765 000024 00000004633 13532474747 020232 0ustar00mukunokistaff000000 000000 #include "mublas_devel.h" #include "mublas_gemv_n_kernel.cu" __host__ int32_t MUBLAS_GEMV ( mublasHandle_t* mh, const char trans, const size_t m, const size_t n, const TYPE0 *alpha, const TYPE0 *a, const size_t lda, const TYPE0 *x, const size_t incx, const TYPE0 *beta, TYPE0 *y, const size_t incy ) { uint32_t kernel_number = 999; void (*kernel) (const SIZE_T, const SIZE_T, const TYPE0, const TYPE0*, const SIZE_T, const TYPE0*, const TYPE0, TYPE0 *); mublasRecipeDefault (mh); uint32_t nonvectorkernel = 0; #if defined (PREC_DX) || defined (PREC_SX) if (*alpha != ONE0 || *beta != ZERO0) { printf ("Non-supported operation: alpha!=1 (%f), beta!=0 (%f)\n", *alpha, *beta); return 0; } #endif mh->m = m; mh->n = n; mh->N_one = sizeof (TYPE0); mh->N_T = 1; if (VEC4) mh->N_T = 4; else if (VEC2) mh->N_T = 2; if ((((long)a%(128/sizeof(TYPE0)))%16 != 0) || (((long)x%(128/sizeof(TYPE0)))%16 != 0) || (((long)y%(128/sizeof(TYPE0)))%16 != 0) || (lda%mh->N_T != 0)) nonvectorkernel = 1; #if defined (PREC_DX) || defined (PREC_SX) mh->N_T = 1; #if defined (PREC_SX) mh->N_T = 2; #endif nonvectorkernel = 0; if (trans == 'T' || trans == 't') { printf ("not supported yet.\n"); return 0; } #endif if (incx == 1 && incy == 1) { if (trans == 'N' || trans == 'n') { mh->BlkDim = 2; mh->func_getShmPerBlk = &getShmPerBlk_GEMV_N; mh->func_getBlkPerGrd = &getBlkPerGrd_GEMV_N; #include "mublas_gemv_n.incl" kernel_number = 100 + mh->N_T * 10 + nonvectorkernel; } else if (trans == 'T' || trans == 't') { } } switch (kernel_number) { case 110: kernel = &MUBLAS_GEMV_N_DEVICE_s1; break; #if !defined (PREC_DX) case 120: kernel = &MUBLAS_GEMV_N_DEVICE_v2; break; #if !defined (PREC_SX) case 140: kernel = &MUBLAS_GEMV_N_DEVICE_v4; break; case 141: kernel = &MUBLAS_GEMV_N_DEVICE_s4; break; case 121: kernel = &MUBLAS_GEMV_N_DEVICE_s2; break; #endif #endif } if (kernel_number == 999) { printf ("mublas error: not implemented"); return 0; } mh->func_cache = cudaFuncCachePreferShared; cudaFuncSetCacheConfig (kernel, mh->func_cache); cudaFuncSetAttribute (kernel, cudaFuncAttributePreferredSharedMemoryCarveout, 100); cudaFuncGetAttributes (&mh->funcatb, kernel); mublas_optimizer (mh); dim3 threads = dim3 (mh->Tx, mh->Ty); dim3 grid = dim3 (mh->Bx, mh->By); kernel <<< grid, threads, mh->ShmPerBlk >>> (m, n, *alpha, a, lda, x, *beta, y); return 0; } blas_dot2_v01a/src/mublas_csrmv_n_kernel.cu000644 000765 000024 00000006340 13532170701 022257 0ustar00mukunokistaff000000 000000 /* *********************************************** CSRMV-N for CUDA *********************************************** */ #define USE_NC_csrValA_CSRMV_N 1 #define USE_NC_csrRowPtrA_CSRMV_N 1 #define USE_NC_csrColIndA_CSRMV_N 1 #if USE_NC_csrValA_CSRMV_N #define RESTRICT_csrValA __restrict__ #define LOAD1_csrValA LOAD1_NC #else #define RESTRICT_csrValA #define LOAD1_csrValA LOAD1___ #endif #if USE_NC_csrRowPtrA_CSRMV_N #define RESTRICT_csrRowPtrA __restrict__ #define LOAD1_csrRowPtrA LOAD1_NC #else #define RESTRICT_csrRowPtrA #define LOAD1_csrRowPtrA LOAD1___ #endif #if USE_NC_csrColIndA_CSRMV_N #define RESTRICT_csrColIndA __restrict__ #define LOAD1_csrColIndA LOAD1_NC #else #define RESTRICT_csrColIndA #define LOAD1_csrColIndA LOAD1___ #endif /* *********************************************** Functions for determining Tx and Ty *********************************************** */ __host__ __inline__ void getBlkPerGrd_CSRMV_N (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; mh->Bx = mh->m / (mh->Tx/mh->N_T) + ((mh->m % (mh->Tx/mh->N_T)) != 0); mh->By = 1; mh->Bz = 1; } __host__ __inline__ void getShmPerBlk_CSRMV_N (void* mh_) { mublasHandle_t* mh = (mublasHandle_t*) mh_; mh->ShmPerBlk = ceilingEx ((float)(WrpSize * mh->N_one * mh->N_T), mh->ShmUnit); } __host__ __inline__ size_t getTxSuf_CSRMV_N (mublasHandle_t* mh) { return (size_t)ceilingEx ((float)mh->n / (float)mh->devprop.multiProcessorCount, mh->TxStep) * WrpSize; } /* *********************************************** kernel=s1, trans=N *********************************************** */ __global__ void MUBLAS_CSRMV_N_DEVICE_N32 ( const SIZE_T m, const TYPE0 alpha, const TYPE0 * RESTRICT_csrValA csrValA, const int32_t * RESTRICT_csrRowPtrA csrRowPtrA, const int32_t * RESTRICT_csrColIndA csrColIndA, const TYPE0 * __restrict__ x, const TYPE0 beta, TYPE0 *y ) { const SIZE_T tx = threadIdx.x; const SIZE_T tid = blockDim.x * blockIdx.x + tx; const SIZE_T rowid = tid / 32; const SIZE_T lane = tid % 32; SIZE_T i; #ifdef PREC_DX register TYPE0 Xr1, Ar1, Yr1; #else register TYPE1 Xr1, Ar1, Yr1; #endif register TYPE1 Tr1; if (rowid < m){ Tr1 = ZERO1; for (i = csrRowPtrA[rowid] + lane; i < csrRowPtrA[rowid+1]; i += 32) { LOAD1_csrValA (Ar1, &csrValA[i]); LOAD1_NC (Xr1, &x[csrColIndA[i]]); #ifdef PREC_DX cuDot2i (Ar1, Xr1, Tr1); #else Tr1 = MAD1 (Ar1, Xr1, Tr1); #endif } // reduction #pragma unroll for (i = 16; i > 0; i >>= 1) { #ifdef PREC_DX double q; cuTwoSum (Tr1.x, shuffleGet (Tr1.x, i), Tr1.x, q); Tr1.y = Tr1.y + (q + shuffleGet (Tr1.y, i)); #else shuffleAdd (Tr1, i); #endif } if (alpha == ONE0 && beta == ZERO0) { if (lane == 0) { #ifdef PREC_DX STORE1___ (&y[rowid], Tr1.x+Tr1.y); #else STORE1___ (&y[rowid], Tr1); #endif } } else { if (lane == 0) { LOAD1___ (Yr1, &y[rowid]); #ifdef PREC_DX Yr1 = MAD1 (LOAD0(alpha), (Tr1.x+Tr1.y), MUL1 (LOAD0(beta), Yr1)); #else Yr1 = MAD1 (LOAD0(alpha), Tr1, MUL1 (LOAD0(beta), Yr1)); #endif STORE1___ (&y[rowid], Yr1); } } } } #undef RESTRICT_csrValA #undef RESTRICT_csrRowPtrA #undef RESTRICT_csrColIndA #undef LOAD1_csrValA #undef LOAD1_csrRowPtrA #undef LOAD1_csrColIndA blas_dot2_v01a/src/.incl000644 000765 000024 00000000067 13531160667 016313 0ustar00mukunokistaff000000 000000 if (mh->cc == 52) { mh->nesBlockOccupancy = 0.1875; } blas_dot2_v01a/src/mublas_dot_kernel_sdot2.cu000644 000765 000024 00000007620 13531674362 022526 0ustar00mukunokistaff000000 000000 /* *********************************************** DOT *********************************************** */ #include "mublas_dot.def" __device__ __forceinline__ void cuBTwoProdFMA (float a, float b, float &p, float &e) { p = __fmul_rn (a, b); e = __fmaf_rn (a, b, -p); } __device__ __forceinline__ void cuBTwoSum (float a, float b, float &s, float &e) { float v; s = __fadd_rn (a, b); v = __fsub_rn (s, a); e = __fadd_rn ( __fsub_rn(a, __fsub_rn (s, v)), __fsub_rn (b, v)); } __device__ __forceinline__ void cuBDot2i (const float a, const float b, float2 &c) { float h, r, q; cuBTwoProdFMA (a, b, h, r); cuBTwoSum (c.x, h, c.x, q); c.y = c.y + (q + r); } /* *********************************************** Macro *********************************************** */ #if USE_NC_X_DOT #define RESTRICT_X __restrict__ #define LOAD1_X LOAD1_NC #define LOAD2_X LOAD2_NC #define LOAD4_X LOAD4_NC #else #define RESTRICT_X #define LOAD1_X LOAD1___ #define LOAD2_X LOAD2___ #define LOAD4_X LOAD4___ #endif #if USE_NC_Y_DOT #define RESTRICT_Y __restrict__ #define LOAD1_Y LOAD1_NC #define LOAD2_Y LOAD2_NC #define LOAD4_Y LOAD4_NC #else #define RESTRICT_Y #define LOAD1_Y LOAD1___ #define LOAD2_Y LOAD2___ #define LOAD4_Y LOAD4___ #endif #define STORE1_Y STORE1___ #define STORE2_Y STORE2___ #define STORE4_Y STORE4___ /* *********************************************** kernel=s1 *********************************************** */ __global__ void MUBLAS_SUM_DEVICE_s1 ( SIZE_T n, TYPE1 *w ) { const int32_t Tx = NTX_SUM;//blockDim.x; const int32_t iTx = threadIdx.x; int32_t i, idx; TYPE1 Wr1, Tr1; __shared__ TYPE1 Ts1[NTX_SUM]; Tr1 = ZERO1; for (idx = iTx; idx < n; idx += Tx) { Wr1 = w[idx]; #ifdef PREC_SX float q; cuBTwoSum (Tr1.x, Wr1.x, Tr1.x, q); Tr1.y = Tr1.y + (q + Wr1.y); #else Tr1 = ADD1 (Wr1, Tr1); #endif } Ts1[iTx] = Tr1; __syncthreads (); #pragma unroll for (i = Tx/2; i >= WrpSize; i >>= 1) { if (iTx < i) { #ifdef PREC_SX float q; cuBTwoSum (Ts1[iTx].x, Ts1[iTx+i].x, Ts1[iTx].x, q); Ts1[iTx].y = Ts1[iTx].y + (q + Ts1[iTx+i].y); #else Ts1[iTx] = ADD1 (Ts1[iTx], Ts1[iTx+i]); #endif } __syncthreads (); } Tr1 = Ts1[iTx]; #pragma unroll for (i = WrpSize/2; i > 0; i >>= 1) { #ifdef PREC_SX float q; cuBTwoSum (Tr1.x, shuffleGet (Tr1.x, i), Tr1.x, q); Tr1.y = Tr1.y + (q + shuffleGet (Tr1.y, i)); #else shuffleAdd (Tr1, i); #endif } if (iTx == 0) { #ifdef PREC_SX STORE1_Y (&w[0].x, (Tr1.x+Tr1.y)); #elif PREC_SX (float&)w[0] = (float)Tr1; #else w[0] = Tr1; #endif } } __global__ void MUBLAS_DOT_DEVICE_s1 ( const SIZE_T n, const TYPE0 * RESTRICT_X x, const TYPE0 * RESTRICT_Y y, TYPE1 *w ) { #if VEC1 const SIZE_T Tx = NTX_DOT;//blockDim.x; const SIZE_T Bx = gridDim.x; const SIZE_T iTx = threadIdx.x; const SIZE_T iBx = blockIdx.x; SIZE_T i, idx; TYPE0 Xr1, Yr1; TYPE1 Tr1; __shared__ TYPE1 Ts1[NTX_DOT]; // Multiply-add Tr1 = ZERO1; for (idx = iBx * Tx + iTx; idx < n; idx += Bx * Tx) { Xr1 = x[idx]; Yr1 = y[idx]; #ifdef PREC_SX cuBDot2i (Xr1, Yr1, Tr1); #else Tr1 = MAD1 (Xr1, Yr1, Tr1); #endif } Ts1[iTx] = Tr1; __syncthreads (); // Reduction #pragma unroll for (i = Tx/2; i >= WrpSize; i >>= 1) { if (iTx < i) { #ifdef PREC_SX float q; cuBTwoSum (Ts1[iTx].x, Ts1[iTx+i].x, Ts1[iTx].x, q); Ts1[iTx].y = Ts1[iTx].y + (q + Ts1[iTx+i].y); #else Ts1[iTx] = ADD1 (Ts1[iTx], Ts1[iTx+i]); #endif } __syncthreads (); } Tr1 = Ts1[iTx]; #pragma unroll for (i = WrpSize/2; i > 0; i >>= 1) { #ifdef PREC_SX float q; cuBTwoSum (Tr1.x, shuffleGet (Tr1.x, i), Tr1.x, q); Tr1.y = Tr1.y + (q + shuffleGet (Tr1.y, i)); #else shuffleAdd (Tr1, i); #endif } if (iTx == 0) w[iBx] = Tr1; #endif } #undef RESTRICT_X #undef LOAD1_X #undef LOAD2_X #undef LOAD4_X #undef RESTRICT_Y #undef LOAD1_Y #undef LOAD2_Y #undef LOAD4_Y #undef STORE1_Y #undef STORE2_Y #undef STORE4_Y blas_dot2_v01a/src/.set000644 000765 000024 00000001044 13531160667 016155 0ustar00mukunokistaff000000 000000 *if (mh->cc == 52) { mh->nesBlockOccupancy = 0.1875; } *mh->nesWarpOccupancy = 0.0; *mh->nesBlockOccupancy = 0.0; *if (30 <= mh->cc && mh->cc < 40) { mh->nesBlockOccupancy = 0.1875; } *mh->nesComputeOccupancy = 0.0; *mh->sfcWarpOccupancy = 0.0; *mh->sfcBlockOccupancy = 0.0; *mh->sfcComputeOccupancy = 1.0; *mh->Th_B_min = 64; *mh->Th_B_max = 1024; *mh->Tx_B_prefer = S; *mh->Ty_B_prefer = S; *mh->max_Ty_B_per_Tx_B_ratio = 6; *mh->B_M_qmax_dim1 = 150; *mh->B_M_qmax_dim2 = 6; *if (mh->cc == 52) { mh->nesBlockOccupancy = 0.1875; } blas_dot2_v01a/src/mublas_gemv_n.incl000644 000765 000024 00000000516 13531160667 021051 0ustar00mukunokistaff000000 000000 /* incl file */ if (mh->cc >= 350) { mh->WrpOcpSuf = 0.4; } if (mh->cc >= 350) { mh->BlkOcpSuf = 0.0; } if (mh->cc >= 350) { mh->GrdOcpSuf = 0.8; } if (mh->cc >= 500) { mh->WrpOcpSuf = 0.4; } if (mh->cc >= 500) { mh->BlkOcpSuf = 0.4; } if (mh->cc >= 500) { mh->GrdOcpSuf = 0.9; } #if defined (PREC_EXD) mh->TxMax = 128; #endif blas_dot2_v01a/eval_jcam2019/_testing_dot_rascal03_check.sh000755 000765 000024 00000003024 13532475771 024703 0ustar00mukunokistaff000000 000000 #!/bin/sh #PBS -l nodes=1:rascal03:ppn=4 cd $PBS_O_WORKDIR step=1024 max=1024000000 iter=10000 stime=1 ../testing/testing_mublas_sdot --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_sdot_check.dat ../testing/testing_mublas_sxdot --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_sxdot_check.dat ../testing/testing_cublas_sdot --mode=c --iter=${iter} --mnk=${step} > _testing_cublas_sdot_check.dat ../testing/testing_mublas_ddot --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_ddot_check.dat ../testing/testing_mublas_dxdot --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_dxdot_check.dat ../testing/testing_cublas_ddot --mode=c --iter=${iter} --mnk=${step} > _testing_cublas_ddot_check.dat for((i=((step+step)); i<=${max}; i*=2)) { echo ${i} ../testing/testing_mublas_sdot --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sdot_check.dat sleep ${stime} ../testing/testing_mublas_sxdot --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sxdot_check.dat sleep ${stime} ../testing/testing_cublas_sdot --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_sdot_check.dat sleep ${stime} ../testing/testing_mublas_ddot --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_ddot_check.dat sleep ${stime} ../testing/testing_mublas_dxdot --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_dxdot_check.dat sleep ${stime} ../testing/testing_cublas_ddot --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_ddot_check.dat sleep ${stime} } blas_dot2_v01a/eval_jcam2019/_testing_mublas_sxgemm_perf.dat000644 000765 000024 00000004404 13532507667 025305 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:53:04 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: SXGEMM # Library: MUBLAS # mode: performance evaluation # # of Iter: 100 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 512 512 512 1.340e-04 2.008e+03 3.129e+01 100 1.208e-02 9.012e+01 2.229e+01 (TITAN V) 1024 1024 1024 4.448e-04 4.835e+03 3.772e+01 100 7.045e-02 1.584e+02 3.053e+01 (TITAN V) 1536 1536 1536 1.320e-03 5.498e+03 2.861e+01 100 2.421e-01 1.835e+02 2.997e+01 (TITAN V) 2048 2048 2048 3.384e-03 5.080e+03 1.983e+01 100 5.837e-01 1.725e+02 2.945e+01 (TITAN V) 2560 2560 2560 5.636e-03 5.957e+03 1.860e+01 100 1.108e+00 1.966e+02 3.031e+01 (TITAN V) 3072 3072 3072 1.027e-02 5.648e+03 1.470e+01 100 1.964e+00 1.912e+02 2.954e+01 (TITAN V) 3584 3584 3584 1.548e-02 5.952e+03 1.328e+01 100 3.229e+00 2.086e+02 2.853e+01 (TITAN V) 4096 4096 4096 2.296e-02 5.989e+03 1.169e+01 100 4.910e+00 2.139e+02 2.800e+01 (TITAN V) 4608 4608 4608 3.337e-02 5.867e+03 1.018e+01 100 7.268e+00 2.178e+02 2.693e+01 (TITAN V) 5120 5120 5120 4.568e-02 5.879e+03 9.183e+00 100 1.013e+01 2.217e+02 2.652e+01 (TITAN V) 5632 5632 5632 6.177e-02 5.786e+03 8.217e+00 100 1.336e+01 2.164e+02 2.674e+01 (TITAN V) 6144 6144 6144 7.987e-02 5.809e+03 7.562e+00 100 1.736e+01 2.174e+02 2.672e+01 (TITAN V) 6656 6656 6656 1.021e-01 5.776e+03 6.941e+00 100 2.200e+01 2.154e+02 2.682e+01 (TITAN V) 7168 7168 7168 1.300e-01 5.665e+03 6.322e+00 100 2.713e+01 2.086e+02 2.716e+01 (TITAN V) 7680 7680 7680 1.624e-01 5.579e+03 5.811e+00 100 3.314e+01 2.041e+02 2.734e+01 (TITAN V) 8192 8192 8192 1.999e-01 5.502e+03 5.372e+00 100 3.927e+01 1.964e+02 2.801e+01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_cublas_dgemv_perf.dat000644 000765 000024 00000004273 13532504712 025065 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:30:43 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: DGEMV # Library: CUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 1024 1024 -- 1.861e-05 1.128e+02 4.520e+02 10000 1.776e-03 9.541e+01 1.183e+00 (TITAN V) 2048 2048 -- 5.626e-05 1.492e+02 5.973e+02 10000 6.015e-03 1.069e+02 1.396e+00 (TITAN V) 3072 3072 -- 1.229e-04 1.536e+02 6.149e+02 10000 1.333e-02 1.084e+02 1.417e+00 (TITAN V) 4096 4096 -- 2.137e-04 1.571e+02 6.286e+02 10000 2.332e-02 1.091e+02 1.439e+00 (TITAN V) 5120 5120 -- 3.286e-04 1.596e+02 6.386e+02 10000 3.633e-02 1.105e+02 1.444e+00 (TITAN V) 6144 6144 -- 4.710e-04 1.603e+02 6.415e+02 10000 5.293e-02 1.124e+02 1.427e+00 (TITAN V) 7168 7168 -- 6.386e-04 1.610e+02 6.439e+02 10000 7.277e-02 1.140e+02 1.412e+00 (TITAN V) 8192 8192 -- 8.330e-04 1.612e+02 6.448e+02 10000 9.638e-02 1.157e+02 1.393e+00 (TITAN V) 9216 9216 -- 1.052e-03 1.616e+02 6.464e+02 10000 1.248e-01 1.187e+02 1.361e+00 (TITAN V) 10240 10240 -- 1.297e-03 1.618e+02 6.471e+02 10000 1.570e-01 1.211e+02 1.336e+00 (TITAN V) 11264 11264 -- 1.568e-03 1.618e+02 6.473e+02 10000 1.919e-01 1.224e+02 1.322e+00 (TITAN V) 12288 12288 -- 1.865e-03 1.620e+02 6.479e+02 10000 2.287e-01 1.226e+02 1.321e+00 (TITAN V) 13312 13312 -- 2.195e-03 1.615e+02 6.459e+02 10000 2.667e-01 1.215e+02 1.329e+00 (TITAN V) 14336 14336 -- 2.548e-03 1.613e+02 6.454e+02 10000 3.129e-01 1.228e+02 1.314e+00 (TITAN V) 15360 15360 -- 2.905e-03 1.624e+02 6.498e+02 10000 3.627e-01 1.248e+02 1.301e+00 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_sgemm_perf.dat000644 000765 000024 00000004375 13532507632 025114 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:53:03 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: SGEMM # Library: MUBLAS # mode: performance evaluation # # of Iter: 100 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 512 512 512 7.780e-05 3.460e+03 5.391e+01 100 0.000e+00 0.000e+00 inf (TITAN V) 1024 1024 1024 2.405e-04 8.942e+03 6.976e+01 100 3.619e-02 1.505e+02 5.943e+01 (TITAN V) 1536 1536 1536 6.484e-04 1.119e+04 5.821e+01 100 1.295e-01 1.997e+02 5.601e+01 (TITAN V) 2048 2048 2048 1.576e-03 1.091e+04 4.258e+01 100 3.123e-01 1.982e+02 5.504e+01 (TITAN V) 2560 2560 2560 3.089e-03 1.087e+04 3.394e+01 100 6.127e-01 1.983e+02 5.480e+01 (TITAN V) 3072 3072 3072 5.110e-03 1.135e+04 2.955e+01 100 1.167e+00 2.283e+02 4.972e+01 (TITAN V) 3584 3584 3584 7.784e-03 1.183e+04 2.640e+01 100 1.851e+00 2.378e+02 4.976e+01 (TITAN V) 4096 4096 4096 1.162e-02 1.183e+04 2.310e+01 100 2.909e+00 2.504e+02 4.726e+01 (TITAN V) 4608 4608 4608 1.681e-02 1.164e+04 2.021e+01 100 4.314e+00 2.566e+02 4.537e+01 (TITAN V) 5120 5120 5120 2.324e-02 1.155e+04 1.805e+01 100 5.948e+00 2.559e+02 4.514e+01 (TITAN V) 5632 5632 5632 3.219e-02 1.110e+04 1.577e+01 100 7.521e+00 2.337e+02 4.752e+01 (TITAN V) 6144 6144 6144 4.201e-02 1.105e+04 1.438e+01 100 9.832e+00 2.341e+02 4.719e+01 (TITAN V) 6656 6656 6656 5.316e-02 1.110e+04 1.333e+01 100 1.251e+01 2.353e+02 4.717e+01 (TITAN V) 7168 7168 7168 6.610e-02 1.115e+04 1.244e+01 100 1.564e+01 2.366e+02 4.710e+01 (TITAN V) 7680 7680 7680 8.315e-02 1.090e+04 1.135e+01 100 1.951e+01 2.346e+02 4.645e+01 (TITAN V) 8192 8192 8192 9.859e-02 1.115e+04 1.089e+01 100 2.329e+01 2.362e+02 4.722e+01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_dxgemv_perf.dat000644 000765 000024 00000004274 13532504643 025273 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:30:42 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: DXGEMV # Library: MUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 1024 1024 -- 2.902e-05 7.236e+01 2.899e+02 10000 2.793e-03 9.623e+01 7.520e-01 (TITAN V) 2048 2048 -- 6.473e-05 1.297e+02 5.191e+02 10000 8.148e-03 1.259e+02 1.030e+00 (TITAN V) 3072 3072 -- 1.375e-04 1.373e+02 5.496e+02 10000 1.797e-02 1.307e+02 1.051e+00 (TITAN V) 4096 4096 -- 2.204e-04 1.523e+02 6.095e+02 10000 3.031e-02 1.375e+02 1.107e+00 (TITAN V) 5120 5120 -- 3.356e-04 1.563e+02 6.253e+02 10000 4.678e-02 1.394e+02 1.121e+00 (TITAN V) 6144 6144 -- 5.002e-04 1.510e+02 6.041e+02 10000 6.923e-02 1.384e+02 1.091e+00 (TITAN V) 7168 7168 -- 6.549e-04 1.570e+02 6.279e+02 10000 9.777e-02 1.493e+02 1.051e+00 (TITAN V) 8192 8192 -- 8.949e-04 1.500e+02 6.001e+02 10000 1.248e-01 1.394e+02 1.076e+00 (TITAN V) 9216 9216 -- 1.080e-03 1.573e+02 6.292e+02 10000 1.641e-01 1.519e+02 1.035e+00 (TITAN V) 10240 10240 -- 1.313e-03 1.597e+02 6.391e+02 10000 2.028e-01 1.545e+02 1.034e+00 (TITAN V) 11264 11264 -- 1.620e-03 1.567e+02 6.268e+02 10000 2.501e-01 1.544e+02 1.015e+00 (TITAN V) 12288 12288 -- 1.893e-03 1.595e+02 6.382e+02 10000 2.825e-01 1.492e+02 1.069e+00 (TITAN V) 13312 13312 -- 2.394e-03 1.480e+02 5.923e+02 10000 3.366e-01 1.406e+02 1.053e+00 (TITAN V) 14336 14336 -- 2.645e-03 1.554e+02 6.218e+02 10000 4.118e-01 1.557e+02 9.982e-01 (TITAN V) 15360 15360 -- 3.001e-03 1.573e+02 6.291e+02 10000 4.721e-01 1.573e+02 9.995e-01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_cublas_scsrmv_perf.dat000644 000765 000024 00000004307 13532512266 025301 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 1.748e-03 1.223e+02 5.011e+02 10000 3.155e-01 1.804e+02 6.779e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 2.762e-04 7.742e+01 3.104e+02 10000 3.112e-02 1.127e+02 6.872e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 1.384e-03 1.314e+02 5.289e+02 10000 2.246e-01 1.623e+02 8.100e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 8.485e-05 9.168e+01 3.699e+02 10000 1.135e-02 1.338e+02 6.852e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 3.633e-05 8.805e+01 3.599e+02 10000 4.530e-03 1.247e+02 7.062e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 4.025e-04 1.432e+02 5.737e+02 10000 5.776e-02 1.435e+02 9.980e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 7.246e-05 1.214e+02 4.877e+02 10000 9.763e-03 1.347e+02 9.012e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 3.473e-05 1.043e+02 4.244e+02 10000 4.569e-03 1.316e+02 7.928e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 2.491e-05 1.007e+02 4.106e+02 10000 3.200e-03 1.285e+02 7.838e-01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_scsrmv_check.dat000644 000765 000024 00000003641 13532503446 025434 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 ### condmax = 5.755e+01 2.680801e-07 1919485 % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 ### condmax = 4.932e+08 5.126100e-01 37270 % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 ### condmax = 3.947e+08 5.671381e-01 769101 % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 ### condmax = 3.869e+05 6.852095e-03 41105 % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 ### condmax = 4.643e+05 5.715374e-04 25483 % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 ### condmax = 1.654e+06 2.802729e-02 59446 % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 ### condmax = 7.364e+05 8.968209e-04 26735 % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 ### condmax = 1.676e+06 1.711181e-02 43842 % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 ### condmax = 2.035e+05 1.182995e-03 35034 blas_dot2_v01a/eval_jcam2019/_testing_cublas_scsrmv_check.dat000644 000765 000024 00000003641 13532503455 025422 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 ### condmax = 5.755e+01 2.680801e-07 1867575 % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 ### condmax = 4.932e+08 8.406626e-03 37797 % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 ### condmax = 3.947e+08 1.342763e-01 771942 % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 ### condmax = 3.869e+05 1.171397e-02 42518 % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 ### condmax = 4.643e+05 2.436054e-04 18563 % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 ### condmax = 1.654e+06 9.101561e-03 59153 % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 ### condmax = 7.364e+05 1.485884e-03 26818 % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 ### condmax = 1.676e+06 1.076678e-02 42724 % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 ### condmax = 2.035e+05 1.501709e-03 34203 blas_dot2_v01a/eval_jcam2019/_testing_mublas_dxcsrmv_check.dat000644 000765 000024 00000003572 13532503464 025610 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 ### condmax = 5.755e+01 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 ### condmax = 3.939e+08 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 ### condmax = 4.948e+08 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 ### condmax = 3.869e+05 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 ### condmax = 4.639e+05 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 ### condmax = 1.652e+06 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 ### condmax = 7.362e+05 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 ### condmax = 1.685e+06 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 ### condmax = 2.035e+05 0.000000e+00 0 blas_dot2_v01a/eval_jcam2019/_testing_cublas_sdot_perf.dat000644 000765 000024 00000005163 13532501265 024733 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 22:56:02 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: SDOT # Library: CUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName -- 1024 -- 1.371e-05 1.494e-01 5.976e-01 10000 5.675e-04 4.140e+01 3.609e-03 (TITAN V) -- 2048 -- 1.395e-05 2.936e-01 1.175e+00 10000 5.465e-04 3.918e+01 7.495e-03 (TITAN V) -- 4096 -- 1.362e-05 6.017e-01 2.407e+00 10000 5.979e-04 4.391e+01 1.370e-02 (TITAN V) -- 8192 -- 1.422e-05 1.152e+00 4.608e+00 10000 5.654e-04 3.975e+01 2.898e-02 (TITAN V) -- 16384 -- 1.395e-05 2.349e+00 9.396e+00 10000 5.594e-04 4.010e+01 5.858e-02 (TITAN V) -- 32768 -- 1.387e-05 4.725e+00 1.890e+01 10000 6.258e-04 4.511e+01 1.047e-01 (TITAN V) -- 65536 -- 2.263e-05 5.792e+00 2.317e+01 10000 9.307e-04 4.112e+01 1.408e-01 (TITAN V) -- 131072 -- 2.174e-05 1.206e+01 4.823e+01 10000 1.070e-03 4.923e+01 2.449e-01 (TITAN V) -- 262144 -- 2.258e-05 2.322e+01 9.288e+01 10000 1.156e-03 5.121e+01 4.534e-01 (TITAN V) -- 524288 -- 2.258e-05 4.644e+01 1.858e+02 10000 1.261e-03 5.582e+01 8.319e-01 (TITAN V) -- 1048576 -- 3.435e-05 6.106e+01 2.442e+02 10000 2.545e-03 7.409e+01 8.242e-01 (TITAN V) -- 2097152 -- 4.360e-05 9.619e+01 3.848e+02 10000 3.911e-03 8.969e+01 1.073e+00 (TITAN V) -- 4194304 -- 7.302e-05 1.149e+02 4.595e+02 10000 7.160e-03 9.806e+01 1.172e+00 (TITAN V) -- 8388608 -- 1.248e-04 1.344e+02 5.378e+02 10000 1.324e-02 1.061e+02 1.267e+00 (TITAN V) -- 16777216 -- 2.275e-04 1.475e+02 5.899e+02 10000 2.600e-02 1.143e+02 1.290e+00 (TITAN V) -- 33554432 -- 4.363e-04 1.538e+02 6.152e+02 10000 5.270e-02 1.208e+02 1.273e+00 (TITAN V) -- 67108864 -- 8.522e-04 1.575e+02 6.299e+02 10000 1.073e-01 1.259e+02 1.251e+00 (TITAN V) -- 134217728 -- 1.687e-03 1.591e+02 6.364e+02 10000 2.211e-01 1.311e+02 1.214e+00 (TITAN V) -- 268435456 -- 3.369e-03 1.594e+02 6.374e+02 10000 4.527e-01 1.344e+02 1.186e+00 (TITAN V) -- 536870912 -- 6.779e-03 1.584e+02 6.336e+02 10000 9.243e-01 1.363e+02 1.162e+00 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_sxdot_perf.dat000644 000765 000024 00000005164 13532501132 025127 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 22:56:02 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: SXDOT # Library: MUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName -- 1024 -- 1.276e-05 1.606e-01 6.422e-01 10000 5.015e-04 3.932e+01 4.084e-03 (TITAN V) -- 2048 -- 1.280e-05 3.200e-01 1.280e+00 10000 5.093e-04 3.979e+01 8.042e-03 (TITAN V) -- 4096 -- 1.237e-05 6.622e-01 2.649e+00 10000 5.386e-04 4.354e+01 1.521e-02 (TITAN V) -- 8192 -- 1.261e-05 1.299e+00 5.198e+00 10000 5.146e-04 4.081e+01 3.184e-02 (TITAN V) -- 16384 -- 1.286e-05 2.549e+00 1.020e+01 10000 5.209e-04 4.052e+01 6.291e-02 (TITAN V) -- 32768 -- 1.235e-05 5.305e+00 2.122e+01 10000 5.714e-04 4.626e+01 1.147e-01 (TITAN V) -- 65536 -- 1.374e-05 9.537e+00 3.815e+01 10000 6.776e-04 4.931e+01 1.934e-01 (TITAN V) -- 131072 -- 2.229e-05 1.176e+01 4.705e+01 10000 1.064e-03 4.776e+01 2.463e-01 (TITAN V) -- 262144 -- 2.163e-05 2.424e+01 9.697e+01 10000 1.095e-03 5.062e+01 4.789e-01 (TITAN V) -- 524288 -- 2.154e-05 4.868e+01 1.947e+02 10000 1.280e-03 5.944e+01 8.190e-01 (TITAN V) -- 1048576 -- 3.177e-05 6.600e+01 2.640e+02 10000 2.556e-03 8.045e+01 8.204e-01 (TITAN V) -- 2097152 -- 4.348e-05 9.646e+01 3.858e+02 10000 4.109e-03 9.450e+01 1.021e+00 (TITAN V) -- 4194304 -- 7.223e-05 1.161e+02 4.645e+02 10000 7.352e-03 1.018e+02 1.141e+00 (TITAN V) -- 8388608 -- 1.216e-04 1.380e+02 5.520e+02 10000 1.389e-02 1.143e+02 1.208e+00 (TITAN V) -- 16777216 -- 2.271e-04 1.478e+02 5.911e+02 10000 2.743e-02 1.208e+02 1.223e+00 (TITAN V) -- 33554432 -- 4.339e-04 1.547e+02 6.186e+02 10000 5.482e-02 1.263e+02 1.224e+00 (TITAN V) -- 67108864 -- 8.518e-04 1.576e+02 6.303e+02 10000 1.122e-01 1.317e+02 1.196e+00 (TITAN V) -- 134217728 -- 1.688e-03 1.590e+02 6.360e+02 10000 2.303e-01 1.364e+02 1.166e+00 (TITAN V) -- 268435456 -- 3.372e-03 1.592e+02 6.368e+02 10000 4.729e-01 1.402e+02 1.135e+00 (TITAN V) -- 536870912 -- 6.784e-03 1.583e+02 6.331e+02 10000 9.656e-01 1.423e+02 1.112e+00 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_sdot_perf.dat000644 000765 000024 00000005163 13532501000 024730 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 22:56:01 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: SDOT # Library: MUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName -- 1024 -- 1.193e-05 1.716e-01 6.866e-01 10000 4.925e-04 4.128e+01 4.158e-03 (TITAN V) -- 2048 -- 1.233e-05 3.322e-01 1.329e+00 10000 5.432e-04 4.406e+01 7.541e-03 (TITAN V) -- 4096 -- 1.241e-05 6.599e-01 2.640e+00 10000 5.401e-04 4.351e+01 1.517e-02 (TITAN V) -- 8192 -- 1.203e-05 1.362e+00 5.446e+00 10000 4.966e-04 4.127e+01 3.299e-02 (TITAN V) -- 16384 -- 1.262e-05 2.597e+00 1.039e+01 10000 5.081e-04 4.027e+01 6.449e-02 (TITAN V) -- 32768 -- 1.284e-05 5.104e+00 2.042e+01 10000 5.377e-04 4.188e+01 1.219e-01 (TITAN V) -- 65536 -- 1.295e-05 1.012e+01 4.049e+01 10000 6.196e-04 4.785e+01 2.115e-01 (TITAN V) -- 131072 -- 2.069e-05 1.267e+01 5.069e+01 10000 9.371e-04 4.530e+01 2.797e-01 (TITAN V) -- 262144 -- 2.151e-05 2.437e+01 9.750e+01 10000 1.116e-03 5.189e+01 4.698e-01 (TITAN V) -- 524288 -- 2.153e-05 4.870e+01 1.948e+02 10000 1.226e-03 5.695e+01 8.551e-01 (TITAN V) -- 1048576 -- 3.196e-05 6.562e+01 2.625e+02 10000 2.453e-03 7.677e+01 8.548e-01 (TITAN V) -- 2097152 -- 4.301e-05 9.751e+01 3.900e+02 10000 3.922e-03 9.119e+01 1.069e+00 (TITAN V) -- 4194304 -- 7.121e-05 1.178e+02 4.712e+02 10000 7.186e-03 1.009e+02 1.167e+00 (TITAN V) -- 8388608 -- 1.205e-04 1.392e+02 5.569e+02 10000 1.342e-02 1.114e+02 1.250e+00 (TITAN V) -- 16777216 -- 2.263e-04 1.483e+02 5.932e+02 10000 2.654e-02 1.173e+02 1.265e+00 (TITAN V) -- 33554432 -- 4.334e-04 1.548e+02 6.194e+02 10000 5.319e-02 1.227e+02 1.262e+00 (TITAN V) -- 67108864 -- 8.511e-04 1.577e+02 6.308e+02 10000 1.086e-01 1.276e+02 1.236e+00 (TITAN V) -- 134217728 -- 1.686e-03 1.592e+02 6.369e+02 10000 2.226e-01 1.320e+02 1.206e+00 (TITAN V) -- 268435456 -- 3.368e-03 1.594e+02 6.376e+02 10000 4.565e-01 1.355e+02 1.176e+00 (TITAN V) -- 536870912 -- 6.780e-03 1.584e+02 6.335e+02 10000 9.314e-01 1.374e+02 1.153e+00 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_sxcsrmv_perf.dat000644 000765 000024 00000004307 13532512257 025503 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 2.439e-03 8.770e+01 3.592e+02 10000 5.026e-01 2.061e+02 4.255e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 1.451e-04 1.474e+02 5.912e+02 10000 2.162e-02 1.490e+02 9.894e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 1.250e-03 1.455e+02 5.857e+02 10000 2.151e-01 1.721e+02 8.457e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 6.295e-05 1.236e+02 4.986e+02 10000 1.011e-02 1.606e+02 7.695e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 3.662e-05 8.735e+01 3.571e+02 10000 6.009e-03 1.641e+02 5.324e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 3.886e-04 1.483e+02 5.941e+02 10000 5.296e-02 1.363e+02 1.089e+00 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 6.343e-05 1.387e+02 5.571e+02 10000 9.440e-03 1.488e+02 9.321e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 3.663e-05 9.892e+01 4.025e+02 10000 5.970e-03 1.630e+02 6.069e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 2.824e-05 8.881e+01 3.621e+02 10000 4.421e-03 1.565e+02 5.674e-01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_scsrmv_perf.dat000644 000765 000024 00000004307 13532512250 025304 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 2.349e-03 9.103e+01 3.729e+02 10000 4.426e-01 1.884e+02 4.831e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 1.450e-04 1.475e+02 5.915e+02 10000 2.066e-02 1.425e+02 1.035e+00 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 1.232e-03 1.476e+02 5.941e+02 10000 1.997e-01 1.621e+02 9.108e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 6.204e-05 1.254e+02 5.059e+02 10000 9.476e-03 1.527e+02 8.209e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 3.531e-05 9.059e+01 3.703e+02 10000 5.467e-03 1.548e+02 5.852e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 3.919e-04 1.471e+02 5.891e+02 10000 5.212e-02 1.330e+02 1.106e+00 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 6.292e-05 1.398e+02 5.617e+02 10000 8.743e-03 1.390e+02 1.006e+00 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 3.593e-05 1.008e+02 4.103e+02 10000 5.352e-03 1.490e+02 6.769e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 2.728e-05 9.194e+01 3.749e+02 10000 3.980e-03 1.459e+02 6.301e-01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_cublas_sgemm_perf.dat000644 000765 000024 00000004375 13532507710 025077 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:53:05 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: SGEMM # Library: CUBLAS # mode: performance evaluation # # of Iter: 100 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 512 512 512 3.174e-05 8.482e+03 1.321e+02 100 0.000e+00 0.000e+00 inf (TITAN V) 1024 1024 1024 2.088e-04 1.030e+04 8.035e+01 100 4.602e-02 2.204e+02 4.673e+01 (TITAN V) 1536 1536 1536 5.828e-04 1.245e+04 6.477e+01 100 1.410e-01 2.418e+02 5.147e+01 (TITAN V) 2048 2048 2048 1.332e-03 1.291e+04 5.038e+01 100 3.033e-01 2.276e+02 5.669e+01 (TITAN V) 2560 2560 2560 2.584e-03 1.299e+04 4.058e+01 100 6.005e-01 2.324e+02 5.591e+01 (TITAN V) 3072 3072 3072 4.766e-03 1.217e+04 3.168e+01 100 9.017e-01 1.892e+02 6.434e+01 (TITAN V) 3584 3584 3584 6.960e-03 1.324e+04 2.953e+01 100 1.507e+00 2.166e+02 6.112e+01 (TITAN V) 4096 4096 4096 1.094e-02 1.256e+04 2.453e+01 100 2.777e+00 2.538e+02 4.950e+01 (TITAN V) 4608 4608 4608 1.496e-02 1.309e+04 2.272e+01 100 3.832e+00 2.562e+02 5.108e+01 (TITAN V) 5120 5120 5120 2.079e-02 1.292e+04 2.018e+01 100 5.300e+00 2.550e+02 5.066e+01 (TITAN V) 5632 5632 5632 2.765e-02 1.293e+04 1.836e+01 100 6.281e+00 2.272e+02 5.690e+01 (TITAN V) 6144 6144 6144 3.503e-02 1.325e+04 1.724e+01 100 8.091e+00 2.310e+02 5.734e+01 (TITAN V) 6656 6656 6656 4.440e-02 1.329e+04 1.596e+01 100 1.069e+01 2.407e+02 5.520e+01 (TITAN V) 7168 7168 7168 5.690e-02 1.295e+04 1.445e+01 100 1.318e+01 2.317e+02 5.588e+01 (TITAN V) 7680 7680 7680 7.172e-02 1.263e+04 1.316e+01 100 1.600e+01 2.231e+02 5.662e+01 (TITAN V) 8192 8192 8192 8.835e-02 1.245e+04 1.215e+01 100 1.861e+01 2.107e+02 5.908e+01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_dgemv_perf.dat000644 000765 000024 00000004273 13532504574 025105 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:30:41 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: DGEMV # Library: MUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 1024 1024 -- 2.121e-05 9.902e+01 3.967e+02 10000 1.934e-03 9.119e+01 1.086e+00 (TITAN V) 2048 2048 -- 5.790e-05 1.450e+02 5.804e+02 10000 6.198e-03 1.071e+02 1.354e+00 (TITAN V) 3072 3072 -- 1.223e-04 1.544e+02 6.180e+02 10000 1.348e-02 1.102e+02 1.401e+00 (TITAN V) 4096 4096 -- 2.118e-04 1.585e+02 6.341e+02 10000 2.375e-02 1.121e+02 1.413e+00 (TITAN V) 5120 5120 -- 3.277e-04 1.600e+02 6.403e+02 10000 3.725e-02 1.137e+02 1.408e+00 (TITAN V) 6144 6144 -- 4.718e-04 1.601e+02 6.404e+02 10000 5.731e-02 1.215e+02 1.318e+00 (TITAN V) 7168 7168 -- 6.409e-04 1.604e+02 6.416e+02 10000 8.013e-02 1.250e+02 1.283e+00 (TITAN V) 8192 8192 -- 8.329e-04 1.612e+02 6.448e+02 10000 1.019e-01 1.223e+02 1.317e+00 (TITAN V) 9216 9216 -- 1.051e-03 1.617e+02 6.467e+02 10000 1.284e-01 1.222e+02 1.323e+00 (TITAN V) 10240 10240 -- 1.293e-03 1.623e+02 6.492e+02 10000 1.628e-01 1.260e+02 1.288e+00 (TITAN V) 11264 11264 -- 1.574e-03 1.613e+02 6.452e+02 10000 2.092e-01 1.329e+02 1.213e+00 (TITAN V) 12288 12288 -- 1.870e-03 1.615e+02 6.463e+02 10000 2.448e-01 1.309e+02 1.234e+00 (TITAN V) 13312 13312 -- 2.190e-03 1.618e+02 6.474e+02 10000 2.708e-01 1.236e+02 1.309e+00 (TITAN V) 14336 14336 -- 2.597e-03 1.583e+02 6.333e+02 10000 3.406e-01 1.312e+02 1.207e+00 (TITAN V) 15360 15360 -- 2.909e-03 1.622e+02 6.489e+02 10000 3.788e-01 1.302e+02 1.246e+00 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_dot_rascal07_perf.sh000755 000765 000024 00000003010 13531675503 024553 0ustar00mukunokistaff000000 000000 #!/bin/sh #PBS -l nodes=1:rascal07:ppn=4 cd $PBS_O_WORKDIR step=1024 max=1024000000 iter=10000 stime=5 ../testing/testing_mublas_sdot --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_sdot_perf.dat ../testing/testing_mublas_sxdot --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_sxdot_perf.dat ../testing/testing_cublas_sdot --mode=p --iter=${iter} --mnk=${step} > _testing_cublas_sdot_perf.dat ../testing/testing_mublas_ddot --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_ddot_perf.dat ../testing/testing_mublas_dxdot --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_dxdot_perf.dat ../testing/testing_cublas_ddot --mode=p --iter=${iter} --mnk=${step} > _testing_cublas_ddot_perf.dat for((i=((step+step)); i<=${max}; i*=2)) { echo ${i} ../testing/testing_mublas_sdot --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sdot_perf.dat sleep ${stime} ../testing/testing_mublas_sxdot --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sxdot_perf.dat sleep ${stime} ../testing/testing_cublas_sdot --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_sdot_perf.dat sleep ${stime} ../testing/testing_mublas_ddot --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_ddot_perf.dat sleep ${stime} ../testing/testing_mublas_dxdot --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_dxdot_perf.dat sleep ${stime} ../testing/testing_cublas_ddot --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_ddot_perf.dat sleep ${stime} } blas_dot2_v01a/eval_jcam2019/_testing_csrmv_rascal06_check.sh000755 000765 000024 00000002226 13531160667 025247 0ustar00mukunokistaff000000 000000 #!/bin/sh #PBS -l nodes=1:rascal06:ppn=4 cd $PBS_O_WORKDIR ARRAY=( cage15 crankseg_1 dielFilterV3real laminar_duct3D lhr71 nd24k pdb1HYS venkat25 xenon1 ) echo "#" > _testing_mublas_scsrmv_check.dat echo "#" > _testing_mublas_sxcsrmv_check.dat echo "#" > _testing_cublas_scsrmv_check.dat echo "#" > _testing_mublas_dcsrmv_check.dat echo "#" > _testing_mublas_dxcsrmv_check.dat echo "#" > _testing_cublas_dcsrmv_check.dat for((i = 0; i<${#ARRAY[*]};i++)) { matrix=${ARRAY[i]} matsrc=/home/mukunoki/matrix/${matrix}.mtx ../testing/testing_mublas_scsrmv --mode=c --mtx=${matsrc} --nodisp=1 >> _testing_mublas_scsrmv_check.dat ../testing/testing_mublas_sxcsrmv --mode=c --mtx=${matsrc} --nodisp=1 >> _testing_mublas_sxcsrmv_check.dat ../testing/testing_cublas_scsrmv --mode=c --mtx=${matsrc} --nodisp=1 >> _testing_cublas_scsrmv_check.dat ../testing/testing_mublas_dcsrmv --mode=c --mtx=${matsrc} --nodisp=1 >> _testing_mublas_dcsrmv_check.dat ../testing/testing_mublas_dxcsrmv --mode=c --mtx=${matsrc} --nodisp=1 >> _testing_mublas_dxcsrmv_check.dat ../testing/testing_cublas_dcsrmv --mode=c --mtx=${matsrc} --nodisp=1 >> _testing_cublas_dcsrmv_check.dat } blas_dot2_v01a/eval_jcam2019/_testing_mublas_sxcsrmv_check.dat000644 000765 000024 00000003572 13532503452 025624 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 ### condmax = 5.755e+01 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 ### condmax = 4.932e+08 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 ### condmax = 3.947e+08 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 ### condmax = 3.869e+05 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 ### condmax = 4.643e+05 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 ### condmax = 1.654e+06 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 ### condmax = 7.364e+05 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 ### condmax = 1.676e+06 0.000000e+00 0 % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 ### condmax = 2.035e+05 0.000000e+00 0 blas_dot2_v01a/eval_jcam2019/_testing_gemv_rascal04_check.sh000755 000765 000024 00000003052 13532475655 025056 0ustar00mukunokistaff000000 000000 #!/bin/sh #PBS -l nodes=1:rascal04:ppn=4 cd $PBS_O_WORKDIR step=2 max=15360 iter=10000 stime=1 ../testing/testing_mublas_sgemv --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_sgemv_check.dat ../testing/testing_mublas_sxgemv --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_sxgemv_check.dat ../testing/testing_cublas_sgemv --mode=c --iter=${iter} --mnk=${step} > _testing_cublas_sgemv_check.dat ../testing/testing_mublas_dgemv --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_dgemv_check.dat ../testing/testing_mublas_dxgemv --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_dxgemv_check.dat ../testing/testing_cublas_dgemv --mode=c --iter=${iter} --mnk=${step} > _testing_cublas_dgemv_check.dat for((i=((step+step)); i<=${max}; i*=${step})) { echo ${i} ../testing/testing_mublas_sgemv --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sgemv_check.dat sleep ${stime} ../testing/testing_mublas_sxgemv --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sxgemv_check.dat sleep ${stime} ../testing/testing_cublas_sgemv --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_sgemv_check.dat sleep ${stime} ../testing/testing_mublas_dgemv --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_dgemv_check.dat sleep ${stime} ../testing/testing_mublas_dxgemv --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_dxgemv_check.dat sleep ${stime} ../testing/testing_cublas_dgemv --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_dgemv_check.dat sleep ${stime} } blas_dot2_v01a/eval_jcam2019/_testing_mublas_dcsrmv_check.dat000644 000765 000024 00000003641 13532503461 025412 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 ### condmax = 5.755e+01 4.496559e-16 1919363 % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 ### condmax = 3.939e+08 6.384894e-10 37130 % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 ### condmax = 4.948e+08 1.172081e-09 770663 % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 ### condmax = 3.869e+05 1.493079e-11 41470 % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 ### condmax = 4.639e+05 7.370136e-13 14761 % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 ### condmax = 1.652e+06 3.285827e-11 59572 % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 ### condmax = 7.362e+05 3.212921e-12 26541 % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 ### condmax = 1.685e+06 1.704542e-11 43742 % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 ### condmax = 2.035e+05 6.547004e-12 34935 blas_dot2_v01a/eval_jcam2019/_testing_gemm_rascal05_check.sh000755 000765 000024 00000003047 13532475674 025053 0ustar00mukunokistaff000000 000000 #!/bin/sh #PBS -l nodes=1:rascal05:ppn=4 cd $PBS_O_WORKDIR step=2 max=8192 iter=100 stime=1 ../testing/testing_mublas_sgemm --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_sgemm_check.dat ../testing/testing_mublas_sxgemm --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_sxgemm_check.dat ../testing/testing_cublas_sgemm --mode=c --iter=${iter} --mnk=${step} > _testing_cublas_sgemm_check.dat ../testing/testing_mublas_dgemm --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_dgemm_check.dat ../testing/testing_mublas_dxgemm --mode=c --iter=${iter} --mnk=${step} > _testing_mublas_dxgemm_check.dat ../testing/testing_cublas_dgemm --mode=c --iter=${iter} --mnk=${step} > _testing_cublas_dgemm_check.dat for((i=((step+step)); i<=${max}; i*=${step})) { echo ${i} ../testing/testing_mublas_sgemm --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sgemm_check.dat sleep ${stime} ../testing/testing_mublas_sxgemm --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sxgemm_check.dat sleep ${stime} ../testing/testing_cublas_sgemm --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_sgemm_check.dat sleep ${stime} ../testing/testing_mublas_dgemm --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_dgemm_check.dat sleep ${stime} ../testing/testing_mublas_dxgemm --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_dxgemm_check.dat sleep ${stime} ../testing/testing_cublas_dgemm --mode=c --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_dgemm_check.dat sleep ${stime} } blas_dot2_v01a/eval_jcam2019/_testing_mublas_dgemm_perf.dat000644 000765 000024 00000004403 13532507745 025072 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:53:05 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: DGEMM # Library: MUBLAS # mode: performance evaluation # # of Iter: 100 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 512 512 512 1.500e-04 1.794e+03 5.591e+01 100 1.441e-02 9.605e+01 1.868e+01 (TITAN V) 1024 1024 1024 4.975e-04 4.323e+03 6.744e+01 100 6.738e-02 1.354e+02 3.192e+01 (TITAN V) 1536 1536 1536 1.350e-03 5.373e+03 5.591e+01 100 2.538e-01 1.880e+02 2.859e+01 (TITAN V) 2048 2048 2048 3.244e-03 5.300e+03 4.138e+01 100 6.108e-01 1.883e+02 2.815e+01 (TITAN V) 2560 2560 2560 5.812e-03 5.777e+03 3.609e+01 100 1.209e+00 2.080e+02 2.778e+01 (TITAN V) 3072 3072 3072 1.033e-02 5.618e+03 2.925e+01 100 2.222e+00 2.152e+02 2.610e+01 (TITAN V) 3584 3584 3584 1.584e-02 5.816e+03 2.595e+01 100 3.622e+00 2.287e+02 2.543e+01 (TITAN V) 4096 4096 4096 2.364e-02 5.815e+03 2.271e+01 100 5.544e+00 2.345e+02 2.480e+01 (TITAN V) 4608 4608 4608 3.391e-02 5.772e+03 2.004e+01 100 8.127e+00 2.396e+02 2.409e+01 (TITAN V) 5120 5120 5120 4.709e-02 5.703e+03 1.782e+01 100 1.137e+01 2.416e+02 2.361e+01 (TITAN V) 5632 5632 5632 6.269e-02 5.701e+03 1.619e+01 100 1.511e+01 2.410e+02 2.366e+01 (TITAN V) 6144 6144 6144 8.189e-02 5.666e+03 1.475e+01 100 1.962e+01 2.396e+02 2.365e+01 (TITAN V) 6656 6656 6656 1.063e-01 5.549e+03 1.334e+01 100 2.450e+01 2.305e+02 2.408e+01 (TITAN V) 7168 7168 7168 1.347e-01 5.471e+03 1.221e+01 100 3.014e+01 2.238e+02 2.444e+01 (TITAN V) 7680 7680 7680 1.702e-01 5.325e+03 1.109e+01 100 3.707e+01 2.178e+02 2.445e+01 (TITAN V) 8192 8192 8192 2.048e-01 5.370e+03 1.049e+01 100 4.453e+01 2.174e+02 2.470e+01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_cublas_sgemv_perf.dat000644 000765 000024 00000004273 13532504525 025106 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:30:40 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: SGEMV # Library: CUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 1024 1024 -- 9.875e-06 2.127e+02 4.260e+02 10000 7.237e-04 7.329e+01 2.902e+00 (TITAN V) 2048 2048 -- 3.141e-05 2.672e+02 5.349e+02 10000 3.599e-03 1.146e+02 2.332e+00 (TITAN V) 3072 3072 -- 6.453e-05 2.926e+02 5.856e+02 10000 7.680e-03 1.190e+02 2.459e+00 (TITAN V) 4096 4096 -- 1.082e-04 3.101e+02 6.204e+02 10000 1.279e-02 1.182e+02 2.624e+00 (TITAN V) 5120 5120 -- 1.668e-04 3.144e+02 6.291e+02 10000 2.011e-02 1.206e+02 2.608e+00 (TITAN V) 6144 6144 -- 2.393e-04 3.156e+02 6.313e+02 10000 2.964e-02 1.239e+02 2.548e+00 (TITAN V) 7168 7168 -- 3.241e-04 3.171e+02 6.344e+02 10000 4.073e-02 1.257e+02 2.523e+00 (TITAN V) 8192 8192 -- 4.209e-04 3.190e+02 6.380e+02 10000 5.349e-02 1.271e+02 2.510e+00 (TITAN V) 9216 9216 -- 5.310e-04 3.200e+02 6.400e+02 10000 6.901e-02 1.300e+02 2.462e+00 (TITAN V) 10240 10240 -- 6.528e-04 3.213e+02 6.427e+02 10000 8.709e-02 1.334e+02 2.408e+00 (TITAN V) 11264 11264 -- 7.932e-04 3.200e+02 6.400e+02 10000 1.093e-01 1.378e+02 2.321e+00 (TITAN V) 12288 12288 -- 9.366e-04 3.225e+02 6.450e+02 10000 1.301e-01 1.389e+02 2.321e+00 (TITAN V) 13312 13312 -- 1.130e-03 3.137e+02 6.274e+02 10000 1.549e-01 1.371e+02 2.288e+00 (TITAN V) 14336 14336 -- 1.280e-03 3.211e+02 6.423e+02 10000 1.790e-01 1.399e+02 2.296e+00 (TITAN V) 15360 15360 -- 1.459e-03 3.235e+02 6.470e+02 10000 2.055e-01 1.408e+02 2.297e+00 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_dcsrmv_perf.dat000644 000765 000024 00000004307 13532512275 025274 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 3.035e-03 7.047e+01 4.398e+02 10000 6.023e-01 1.985e+02 3.551e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 2.271e-04 9.417e+01 5.673e+02 10000 3.126e-02 1.376e+02 6.842e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 1.857e-03 9.799e+01 5.939e+02 10000 2.911e-01 1.568e+02 6.249e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 8.603e-05 9.042e+01 5.504e+02 10000 1.278e-02 1.486e+02 6.086e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 4.442e-05 7.201e+01 4.479e+02 10000 7.015e-03 1.579e+02 4.560e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 6.010e-04 9.592e+01 5.767e+02 10000 7.884e-02 1.312e+02 7.312e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 9.348e-05 9.413e+01 5.687e+02 10000 1.292e-02 1.382e+02 6.812e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 4.797e-05 7.552e+01 4.661e+02 10000 6.987e-03 1.457e+02 5.185e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 3.521e-05 7.122e+01 4.411e+02 10000 5.424e-03 1.540e+02 4.624e-01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_dot_1080_rascal07_perf.sh000755 000765 000024 00000004031 13531735145 025226 0ustar00mukunokistaff000000 000000 #!/bin/sh #PBS -l nodes=1:rascal07:ppn=4 cd $PBS_O_WORKDIR step=1024 max=1024000000 iter=10000 stime=5 #../testing/testing_mublas_sxdot --mode=p --devno=1 --iter=${iter} --mnk=${step} > _testing_mublas_sxdot_sdot2_perf_gtx1080ti.dat #../testing/testing_mublas_sxdot --mode=p --devno=1 --iter=${iter} --mnk=${step} > _testing_mublas_sxdot_perf_gtx1080ti.dat #../testing/testing_mublas_sdot --mode=p --devno=1 --iter=${iter} --mnk=${step} > _testing_mublas_sdot_perf_gtx1080ti.dat #../testing/testing_cublas_sdot --mode=p --devno=1 --iter=${iter} --mnk=${step} > _testing_cublas_sdot_perf_gtx1080ti.dat #../testing/testing_mublas_ddot --mode=p --devno=1 --iter=${iter} --mnk=${step} > _testing_mublas_ddot_perf_gtx1080ti.dat #../testing/testing_mublas_dxdot --mode=p --devno=1 --iter=${iter} --mnk=${step} > _testing_mublas_dxdot_perf_gtx1080ti.dat #../testing/testing_cublas_ddot --mode=p --devno=1 --iter=${iter} --mnk=${step} > _testing_cublas_ddot_perf_gtx1080ti.dat for((i=((step+step)); i<=${max}; i*=2)) { echo ${i} #../testing/testing_mublas_sxdot --mode=p --devno=1 --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sxdot_sdot2_perf_gtx1080ti.dat #../testing/testing_mublas_sxdot --mode=p --devno=1 --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sxdot_perf_gtx1080ti.dat #sleep ${stime} #../testing/testing_mublas_sdot --mode=p --devno=1 --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sdot_perf_gtx1080ti.dat #sleep ${stime} #../testing/testing_cublas_sdot --mode=p --devno=1 --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_sdot_perf_gtx1080ti.dat #sleep ${stime} #../testing/testing_mublas_ddot --mode=p --devno=1 --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_ddot_perf_gtx1080ti.dat #sleep ${stime} #../testing/testing_mublas_dxdot --mode=p --devno=1 --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_dxdot_perf_gtx1080ti.dat #sleep ${stime} #../testing/testing_cublas_ddot --mode=p --devno=1 --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_ddot_perf_gtx1080ti.dat #sleep ${stime} } blas_dot2_v01a/eval_jcam2019/_testing_gemv_rascal07_perf.sh000755 000765 000024 00000003041 13532135046 024721 0ustar00mukunokistaff000000 000000 #!/bin/sh #PBS -l nodes=1:rascal07:ppn=4 cd $PBS_O_WORKDIR step=1024 max=15360 iter=10000 stime=5 ../testing/testing_mublas_sgemv --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_sgemv_perf.dat ../testing/testing_mublas_sxgemv --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_sxgemv_perf.dat ../testing/testing_cublas_sgemv --mode=p --iter=${iter} --mnk=${step} > _testing_cublas_sgemv_perf.dat ../testing/testing_mublas_dgemv --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_dgemv_perf.dat ../testing/testing_mublas_dxgemv --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_dxgemv_perf.dat ../testing/testing_cublas_dgemv --mode=p --iter=${iter} --mnk=${step} > _testing_cublas_dgemv_perf.dat for((i=((step+step)); i<=${max}; i+=${step})) { echo ${i} ../testing/testing_mublas_sgemv --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sgemv_perf.dat sleep ${stime} ../testing/testing_mublas_sxgemv --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sxgemv_perf.dat sleep ${stime} ../testing/testing_cublas_sgemv --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_sgemv_perf.dat sleep ${stime} ../testing/testing_mublas_dgemv --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_dgemv_perf.dat sleep ${stime} ../testing/testing_mublas_dxgemv --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_dxgemv_perf.dat sleep ${stime} ../testing/testing_cublas_dgemv --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_dgemv_perf.dat sleep ${stime} } blas_dot2_v01a/eval_jcam2019/_testing_csrmv_rascal07_perf.sh000755 000765 000024 00000002500 13531467144 025122 0ustar00mukunokistaff000000 000000 #!/bin/sh #PBS -l nodes=1:rascal07:ppn=4 cd $PBS_O_WORKDIR ARRAY=( cage15 crankseg_1 dielFilterV3real laminar_duct3D lhr71 nd24k pdb1HYS venkat25 xenon1 ) echo "#" > _testing_mublas_scsrmv_perf.dat echo "#" > _testing_mublas_sxcsrmv_perf.dat echo "#" > _testing_cublas_scsrmv_perf.dat echo "#" > _testing_mublas_dcsrmv_perf.dat echo "#" > _testing_mublas_dxcsrmv_perf.dat echo "#" > _testing_cublas_dcsrmv_perf.dat stime=5 for((i = 0; i<${#ARRAY[*]};i++)) { matrix=${ARRAY[i]} matsrc=/home/mukunoki/matrix/${matrix}.mtx ../testing/testing_mublas_scsrmv --mode=p --iter=10000 --mtx=${matsrc} --nodisp=1 >> _testing_mublas_scsrmv_perf.dat sleep ${stime} ../testing/testing_mublas_sxcsrmv --mode=p --iter=10000 --mtx=${matsrc} --nodisp=1 >> _testing_mublas_sxcsrmv_perf.dat sleep ${stime} ../testing/testing_cublas_scsrmv --mode=p --iter=10000 --mtx=${matsrc} --nodisp=1 >> _testing_cublas_scsrmv_perf.dat sleep ${stime} ../testing/testing_mublas_dcsrmv --mode=p --iter=10000 --mtx=${matsrc} --nodisp=1 >> _testing_mublas_dcsrmv_perf.dat sleep ${stime} ../testing/testing_mublas_dxcsrmv --mode=p --iter=10000 --mtx=${matsrc} --nodisp=1 >> _testing_mublas_dxcsrmv_perf.dat sleep ${stime} ../testing/testing_cublas_dcsrmv --mode=p --iter=10000 --mtx=${matsrc} --nodisp=1 >> _testing_cublas_dcsrmv_perf.dat sleep ${stime} } blas_dot2_v01a/eval_jcam2019/_testing_mublas_ddot_perf.dat000644 000765 000024 00000005163 13532501520 024720 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 22:56:03 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: DDOT # Library: MUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName -- 1024 -- 1.244e-05 1.647e-01 1.317e+00 10000 5.255e-04 4.225e+01 3.897e-03 (TITAN V) -- 2048 -- 1.283e-05 3.192e-01 2.553e+00 10000 5.197e-04 4.050e+01 7.881e-03 (TITAN V) -- 4096 -- 1.236e-05 6.626e-01 5.301e+00 10000 5.517e-04 4.462e+01 1.485e-02 (TITAN V) -- 8192 -- 1.263e-05 1.297e+00 1.038e+01 10000 5.133e-04 4.063e+01 3.192e-02 (TITAN V) -- 16384 -- 1.276e-05 2.568e+00 2.055e+01 10000 5.237e-04 4.105e+01 6.257e-02 (TITAN V) -- 32768 -- 1.248e-05 5.249e+00 4.199e+01 10000 5.817e-04 4.659e+01 1.127e-01 (TITAN V) -- 65536 -- 2.104e-05 6.230e+00 4.984e+01 10000 9.054e-04 4.304e+01 1.448e-01 (TITAN V) -- 131072 -- 2.150e-05 1.219e+01 9.754e+01 10000 1.130e-03 5.258e+01 2.319e-01 (TITAN V) -- 262144 -- 2.150e-05 2.439e+01 1.951e+02 10000 1.208e-03 5.618e+01 4.341e-01 (TITAN V) -- 524288 -- 3.325e-05 3.154e+01 2.523e+02 10000 2.265e-03 6.811e+01 4.630e-01 (TITAN V) -- 1048576 -- 4.627e-05 4.532e+01 3.626e+02 10000 3.761e-03 8.128e+01 5.575e-01 (TITAN V) -- 2097152 -- 6.828e-05 6.143e+01 4.915e+02 10000 6.339e-03 9.285e+01 6.616e-01 (TITAN V) -- 4194304 -- 1.226e-04 6.841e+01 5.473e+02 10000 1.195e-02 9.743e+01 7.021e-01 (TITAN V) -- 8388608 -- 2.239e-04 7.495e+01 5.996e+02 10000 2.297e-02 1.026e+02 7.305e-01 (TITAN V) -- 16777216 -- 4.301e-04 7.802e+01 6.242e+02 10000 4.597e-02 1.069e+02 7.299e-01 (TITAN V) -- 33554432 -- 8.451e-04 7.941e+01 6.353e+02 10000 9.189e-02 1.087e+02 7.303e-01 (TITAN V) -- 67108864 -- 1.672e-03 8.029e+01 6.423e+02 10000 1.867e-01 1.117e+02 7.189e-01 (TITAN V) -- 134217728 -- 3.327e-03 8.069e+01 6.455e+02 10000 3.812e-01 1.146e+02 7.042e-01 (TITAN V) -- 268435456 -- 6.644e-03 8.081e+01 6.465e+02 10000 7.739e-01 1.165e+02 6.938e-01 (TITAN V) -- 536870912 -- 1.327e-02 8.089e+01 6.472e+02 10000 1.568e+00 1.181e+02 6.848e-01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_dxgemm_perf.dat000644 000765 000024 00000004404 13532510252 025246 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:53:06 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: DXGEMM # Library: MUBLAS # mode: performance evaluation # # of Iter: 100 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 512 512 512 4.338e-04 6.206e+02 1.934e+01 100 7.014e-02 1.617e+02 3.838e+00 (TITAN V) 1024 1024 1024 3.452e-03 6.231e+02 9.722e+00 100 5.948e-01 1.723e+02 3.616e+00 (TITAN V) 1536 1536 1536 1.107e-02 6.555e+02 6.821e+00 100 2.132e+00 1.926e+02 3.403e+00 (TITAN V) 2048 2048 2048 2.600e-02 6.612e+02 5.162e+00 100 5.004e+00 1.924e+02 3.436e+00 (TITAN V) 2560 2560 2560 5.067e-02 6.626e+02 4.139e+00 100 9.928e+00 1.959e+02 3.382e+00 (TITAN V) 3072 3072 3072 8.735e-02 6.641e+02 3.457e+00 100 1.728e+01 1.978e+02 3.358e+00 (TITAN V) 3584 3584 3584 1.386e-01 6.645e+02 2.965e+00 100 2.783e+01 2.008e+02 3.310e+00 (TITAN V) 4096 4096 4096 2.068e-01 6.649e+02 2.596e+00 100 4.217e+01 2.040e+02 3.260e+00 (TITAN V) 4608 4608 4608 3.050e-01 6.418e+02 2.228e+00 100 5.903e+01 1.936e+02 3.316e+00 (TITAN V) 5120 5120 5120 4.336e-01 6.193e+02 1.935e+00 100 7.909e+01 1.824e+02 3.395e+00 (TITAN V) 5632 5632 5632 5.873e-01 6.085e+02 1.728e+00 100 1.040e+02 1.771e+02 3.436e+00 (TITAN V) 6144 6144 6144 7.665e-01 6.053e+02 1.576e+00 100 1.348e+02 1.758e+02 3.443e+00 (TITAN V) 6656 6656 6656 9.796e-01 6.022e+02 1.447e+00 100 1.709e+02 1.745e+02 3.451e+00 (TITAN V) 7168 7168 7168 1.228e+00 5.999e+02 1.339e+00 100 2.134e+02 1.737e+02 3.453e+00 (TITAN V) 7680 7680 7680 1.513e+00 5.991e+02 1.248e+00 100 2.619e+02 1.731e+02 3.460e+00 (TITAN V) 8192 8192 8192 1.836e+00 5.991e+02 1.170e+00 100 3.171e+02 1.727e+02 3.468e+00 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_dxcsrmv_perf.dat000644 000765 000024 00000004307 13532512303 025454 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 3.480e-03 6.146e+01 3.836e+02 10000 7.756e-01 2.229e+02 2.757e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 2.313e-04 9.244e+01 5.570e+02 10000 3.652e-02 1.579e+02 5.856e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 1.901e-03 9.571e+01 5.800e+02 10000 3.668e-01 1.929e+02 4.960e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 8.828e-05 8.812e+01 5.363e+02 10000 1.672e-02 1.894e+02 4.652e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 5.584e-05 5.729e+01 3.563e+02 10000 1.022e-02 1.830e+02 3.130e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 6.006e-04 9.598e+01 5.771e+02 10000 8.962e-02 1.492e+02 6.432e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 9.635e-05 9.132e+01 5.517e+02 10000 1.566e-02 1.626e+02 5.617e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 4.881e-05 7.423e+01 4.582e+02 10000 9.968e-03 2.042e+02 3.634e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 3.802e-05 6.597e+01 4.086e+02 10000 6.966e-03 1.832e+02 3.600e-01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_sxgemv_perf.dat000644 000765 000024 00000004274 13532504474 025314 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:30:40 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: SXGEMV # Library: MUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 1024 1024 -- 1.639e-05 1.282e+02 2.567e+02 10000 1.112e-03 6.786e+01 1.889e+00 (TITAN V) 2048 2048 -- 3.506e-05 2.395e+02 4.793e+02 10000 3.987e-03 1.137e+02 2.105e+00 (TITAN V) 3072 3072 -- 6.611e-05 2.856e+02 5.715e+02 10000 7.969e-03 1.205e+02 2.370e+00 (TITAN V) 4096 4096 -- 1.102e-04 3.047e+02 6.095e+02 10000 1.386e-02 1.258e+02 2.422e+00 (TITAN V) 5120 5120 -- 1.683e-04 3.116e+02 6.235e+02 10000 2.180e-02 1.295e+02 2.406e+00 (TITAN V) 6144 6144 -- 2.439e-04 3.096e+02 6.193e+02 10000 3.166e-02 1.298e+02 2.385e+00 (TITAN V) 7168 7168 -- 3.274e-04 3.139e+02 6.279e+02 10000 4.354e-02 1.330e+02 2.361e+00 (TITAN V) 8192 8192 -- 4.231e-04 3.173e+02 6.346e+02 10000 5.655e-02 1.336e+02 2.374e+00 (TITAN V) 9216 9216 -- 5.344e-04 3.179e+02 6.360e+02 10000 7.217e-02 1.351e+02 2.354e+00 (TITAN V) 10240 10240 -- 6.544e-04 3.205e+02 6.411e+02 10000 8.925e-02 1.364e+02 2.350e+00 (TITAN V) 11264 11264 -- 7.976e-04 3.182e+02 6.365e+02 10000 1.100e-01 1.380e+02 2.306e+00 (TITAN V) 12288 12288 -- 9.390e-04 3.216e+02 6.434e+02 10000 1.359e-01 1.448e+02 2.222e+00 (TITAN V) 13312 13312 -- 1.115e-03 3.178e+02 6.356e+02 10000 1.528e-01 1.370e+02 2.319e+00 (TITAN V) 14336 14336 -- 1.279e-03 3.215e+02 6.431e+02 10000 1.864e-01 1.458e+02 2.206e+00 (TITAN V) 15360 15360 -- 1.462e-03 3.229e+02 6.458e+02 10000 2.171e-01 1.486e+02 2.173e+00 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_cublas_dcsrmv_perf.dat000644 000765 000024 00000004307 13532512312 025252 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 2.816e-03 7.594e+01 4.739e+02 10000 4.510e-01 1.601e+02 4.742e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 3.180e-04 6.724e+01 4.051e+02 10000 3.776e-02 1.187e+02 5.663e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 2.044e-03 8.901e+01 5.394e+02 10000 3.196e-01 1.564e+02 5.692e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 1.204e-04 6.462e+01 3.933e+02 10000 1.518e-02 1.261e+02 5.124e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 4.706e-05 6.797e+01 4.228e+02 10000 6.312e-03 1.341e+02 5.068e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 5.751e-04 1.002e+02 6.027e+02 10000 8.092e-02 1.407e+02 7.124e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 9.918e-05 8.872e+01 5.360e+02 10000 1.365e-02 1.376e+02 6.445e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 5.262e-05 6.884e+01 4.249e+02 10000 6.857e-03 1.303e+02 5.283e-01 (TITAN V) % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 3.484e-05 7.198e+01 4.458e+02 10000 4.629e-03 1.329e+02 5.418e-01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_gemm_rascal07_perf.sh000755 000765 000024 00000003035 13532660043 024713 0ustar00mukunokistaff000000 000000 #!/bin/sh #PBS -l nodes=1:rascal07:ppn=4 cd $PBS_O_WORKDIR step=512 max=8192 iter=100 stime=5 ../testing/testing_mublas_sgemm --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_sgemm_perf.dat ../testing/testing_mublas_sxgemm --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_sxgemm_perf.dat ../testing/testing_cublas_sgemm --mode=p --iter=${iter} --mnk=${step} > _testing_cublas_sgemm_perf.dat ../testing/testing_mublas_dgemm --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_dgemm_perf.dat ../testing/testing_mublas_dxgemm --mode=p --iter=${iter} --mnk=${step} > _testing_mublas_dxgemm_perf.dat ../testing/testing_cublas_dgemm --mode=p --iter=${iter} --mnk=${step} > _testing_cublas_dgemm_perf.dat for((i=((step+step)); i<=${max}; i+=${step})) { echo ${i} ../testing/testing_mublas_sgemm --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sgemm_perf.dat sleep ${stime} ../testing/testing_mublas_sxgemm --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_sxgemm_perf.dat sleep ${stime} ../testing/testing_cublas_sgemm --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_sgemm_perf.dat sleep ${stime} ../testing/testing_mublas_dgemm --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_dgemm_perf.dat sleep ${stime} ../testing/testing_mublas_dxgemm --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_mublas_dxgemm_perf.dat sleep ${stime} ../testing/testing_cublas_dgemm --mode=p --iter=${iter} --mnk=${i} --nodisp=1 >> _testing_cublas_dgemm_perf.dat sleep ${stime} } blas_dot2_v01a/eval_jcam2019/_testing_mublas_dxdot_perf.dat000644 000765 000024 00000005164 13532501754 025122 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 22:56:04 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: DXDOT # Library: MUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName -- 1024 -- 1.271e-05 1.612e-01 1.289e+00 10000 5.295e-04 4.167e+01 3.868e-03 (TITAN V) -- 2048 -- 1.289e-05 3.178e-01 2.542e+00 10000 5.089e-04 3.948e+01 8.049e-03 (TITAN V) -- 4096 -- 1.211e-05 6.763e-01 5.411e+00 10000 5.345e-04 4.413e+01 1.533e-02 (TITAN V) -- 8192 -- 1.304e-05 1.256e+00 1.005e+01 10000 5.306e-04 4.068e+01 3.088e-02 (TITAN V) -- 16384 -- 1.355e-05 2.419e+00 1.935e+01 10000 5.994e-04 4.424e+01 5.467e-02 (TITAN V) -- 32768 -- 1.871e-05 3.503e+00 2.802e+01 10000 9.096e-04 4.862e+01 7.205e-02 (TITAN V) -- 65536 -- 2.160e-05 6.069e+00 4.855e+01 10000 1.023e-03 4.735e+01 1.282e-01 (TITAN V) -- 131072 -- 2.052e-05 1.278e+01 1.022e+02 10000 1.289e-03 6.282e+01 2.034e-01 (TITAN V) -- 262144 -- 2.154e-05 2.434e+01 1.948e+02 10000 1.459e-03 6.775e+01 3.593e-01 (TITAN V) -- 524288 -- 3.296e-05 3.181e+01 2.545e+02 10000 2.705e-03 8.207e+01 3.877e-01 (TITAN V) -- 1048576 -- 4.605e-05 4.554e+01 3.644e+02 10000 4.186e-03 9.090e+01 5.010e-01 (TITAN V) -- 2097152 -- 7.273e-05 5.767e+01 4.614e+02 10000 7.234e-03 9.946e+01 5.798e-01 (TITAN V) -- 4194304 -- 1.212e-04 6.919e+01 5.535e+02 10000 1.312e-02 1.082e+02 6.395e-01 (TITAN V) -- 8388608 -- 2.268e-04 7.398e+01 5.919e+02 10000 2.547e-02 1.123e+02 6.587e-01 (TITAN V) -- 16777216 -- 4.330e-04 7.749e+01 6.199e+02 10000 5.041e-02 1.164e+02 6.656e-01 (TITAN V) -- 33554432 -- 8.477e-04 7.917e+01 6.333e+02 10000 1.015e-01 1.198e+02 6.609e-01 (TITAN V) -- 67108864 -- 1.674e-03 8.016e+01 6.413e+02 10000 2.063e-01 1.232e+02 6.505e-01 (TITAN V) -- 134217728 -- 3.334e-03 8.051e+01 6.441e+02 10000 4.207e-01 1.262e+02 6.381e-01 (TITAN V) -- 268435456 -- 6.655e-03 8.067e+01 6.454e+02 10000 8.528e-01 1.281e+02 6.296e-01 (TITAN V) -- 536870912 -- 1.329e-02 8.082e+01 6.466e+02 10000 1.728e+00 1.301e+02 6.213e-01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_cublas_ddot_perf.dat000644 000765 000024 00000005163 13532502211 024704 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 22:56:05 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: DDOT # Library: CUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName -- 1024 -- 1.364e-05 1.501e-01 1.201e+00 10000 5.961e-04 4.369e+01 3.436e-03 (TITAN V) -- 2048 -- 1.359e-05 3.014e-01 2.411e+00 10000 5.873e-04 4.322e+01 6.974e-03 (TITAN V) -- 4096 -- 1.300e-05 6.301e-01 5.040e+00 10000 5.668e-04 4.359e+01 1.445e-02 (TITAN V) -- 8192 -- 1.391e-05 1.178e+00 9.426e+00 10000 5.646e-04 4.060e+01 2.902e-02 (TITAN V) -- 16384 -- 1.439e-05 2.277e+00 1.821e+01 10000 6.096e-04 4.236e+01 5.375e-02 (TITAN V) -- 32768 -- 1.395e-05 4.698e+00 3.759e+01 10000 6.402e-04 4.590e+01 1.024e-01 (TITAN V) -- 65536 -- 2.209e-05 5.933e+00 4.747e+01 10000 9.745e-04 4.411e+01 1.345e-01 (TITAN V) -- 131072 -- 2.251e-05 1.165e+01 9.318e+01 10000 1.093e-03 4.857e+01 2.398e-01 (TITAN V) -- 262144 -- 2.260e-05 2.319e+01 1.856e+02 10000 1.178e-03 5.213e+01 4.449e-01 (TITAN V) -- 524288 -- 3.314e-05 3.165e+01 2.532e+02 10000 2.280e-03 6.880e+01 4.600e-01 (TITAN V) -- 1048576 -- 4.517e-05 4.643e+01 3.715e+02 10000 3.513e-03 7.778e+01 5.970e-01 (TITAN V) -- 2097152 -- 7.272e-05 5.768e+01 4.614e+02 10000 6.379e-03 8.772e+01 6.576e-01 (TITAN V) -- 4194304 -- 1.224e-04 6.855e+01 5.484e+02 10000 1.176e-02 9.608e+01 7.134e-01 (TITAN V) -- 8388608 -- 2.275e-04 7.374e+01 5.899e+02 10000 2.291e-02 1.007e+02 7.322e-01 (TITAN V) -- 16777216 -- 4.355e-04 7.704e+01 6.163e+02 10000 4.557e-02 1.046e+02 7.363e-01 (TITAN V) -- 33554432 -- 8.532e-04 7.866e+01 6.293e+02 10000 9.191e-02 1.077e+02 7.301e-01 (TITAN V) -- 67108864 -- 1.694e-03 7.921e+01 6.337e+02 10000 1.877e-01 1.108e+02 7.149e-01 (TITAN V) -- 134217728 -- 3.381e-03 7.939e+01 6.351e+02 10000 3.842e-01 1.136e+02 6.986e-01 (TITAN V) -- 268435456 -- 6.747e-03 7.957e+01 6.365e+02 10000 7.784e-01 1.154e+02 6.897e-01 (TITAN V) -- 536870912 -- 1.345e-02 7.981e+01 6.385e+02 10000 1.567e+00 1.165e+02 6.852e-01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_mublas_sgemv_perf.dat000644 000765 000024 00000004273 13532504444 025120 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:30:39 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: SGEMV # Library: MUBLAS # mode: performance evaluation # # of Iter: 10000 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 1024 1024 -- 2.219e-05 9.466e+01 1.896e+02 10000 1.285e-03 5.790e+01 1.635e+00 (TITAN V) 2048 2048 -- 3.421e-05 2.454e+02 4.911e+02 10000 3.722e-03 1.088e+02 2.256e+00 (TITAN V) 3072 3072 -- 6.371e-05 2.964e+02 5.931e+02 10000 7.330e-03 1.151e+02 2.576e+00 (TITAN V) 4096 4096 -- 1.090e-04 3.080e+02 6.162e+02 10000 1.272e-02 1.167e+02 2.639e+00 (TITAN V) 5120 5120 -- 1.668e-04 3.144e+02 6.289e+02 10000 2.002e-02 1.200e+02 2.620e+00 (TITAN V) 6144 6144 -- 2.379e-04 3.174e+02 6.349e+02 10000 2.969e-02 1.248e+02 2.544e+00 (TITAN V) 7168 7168 -- 3.212e-04 3.199e+02 6.400e+02 10000 4.007e-02 1.247e+02 2.565e+00 (TITAN V) 8192 8192 -- 4.175e-04 3.216e+02 6.433e+02 10000 5.367e-02 1.286e+02 2.501e+00 (TITAN V) 9216 9216 -- 5.268e-04 3.225e+02 6.451e+02 10000 6.966e-02 1.322e+02 2.439e+00 (TITAN V) 10240 10240 -- 6.488e-04 3.233e+02 6.467e+02 10000 8.786e-02 1.354e+02 2.387e+00 (TITAN V) 11264 11264 -- 7.875e-04 3.223e+02 6.446e+02 10000 1.075e-01 1.365e+02 2.362e+00 (TITAN V) 12288 12288 -- 9.364e-04 3.225e+02 6.451e+02 10000 1.273e-01 1.360e+02 2.372e+00 (TITAN V) 13312 13312 -- 1.104e-03 3.211e+02 6.423e+02 10000 1.513e-01 1.370e+02 2.343e+00 (TITAN V) 14336 14336 -- 1.295e-03 3.174e+02 6.349e+02 10000 1.789e-01 1.381e+02 2.298e+00 (TITAN V) 15360 15360 -- 1.465e-03 3.221e+02 6.443e+02 10000 2.003e-01 1.367e+02 2.356e+00 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_cublas_dgemm_perf.dat000644 000765 000024 00000004375 13532510304 025051 0ustar00mukunokistaff000000 000000 # Testing info ----------------------------- # Date: Sat Aug 31 23:53:06 JST 2019 # CPU:model name : Intel(R) Xeon(R) W-2123 CPU @ 3.60GHz # OS: Linux rascal07 3.10.0-693.2.2.el7.x86_64 #1 SMP Tue Sep 12 22:26:13 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux # Host: rascal07 # Device[0] TITAN V # - Theoretical Peak Memory Bandwidth: 652.8 [GB/s] # - Theoretical Peak Performance (SP): 14899.2 [GFlops] # - Theoretical Peak Performance (DP): 7449.6 [GFlops] # - Total Gmem: 12.6 [GB] # - CC: 7.0 # - ECC Enabled: 0 # - MultiProcessorCount: 80 # Driver / Runtime: 10000, 10000 # Routine: DGEMM # Library: CUBLAS # mode: performance evaluation # # of Iter: 100 # BLAS parameter --------------------------- # tranA: N # tranB: N # cublaspointer: HOST # Evaluation result ------------------------ # M N K Time[sec] Perf[GOps/s] Perf[GB/s] #ofItr Energy[J] Power[W] [GOps/W] DevName 512 512 512 9.592e-05 2.807e+03 8.745e+01 100 0.000e+00 0.000e+00 inf (TITAN V) 1024 1024 1024 4.218e-04 5.099e+03 7.955e+01 100 6.659e-02 1.579e+02 3.230e+01 (TITAN V) 1536 1536 1536 1.390e-03 5.220e+03 5.432e+01 100 2.129e-01 1.532e+02 3.408e+01 (TITAN V) 2048 2048 2048 3.101e-03 5.544e+03 4.328e+01 100 5.463e-01 1.762e+02 3.147e+01 (TITAN V) 2560 2560 2560 4.967e-03 6.759e+03 4.222e+01 100 1.043e+00 2.100e+02 3.218e+01 (TITAN V) 3072 3072 3072 9.474e-03 6.123e+03 3.188e+01 100 1.894e+00 1.999e+02 3.063e+01 (TITAN V) 3584 3584 3584 1.397e-02 6.593e+03 2.942e+01 100 2.969e+00 2.125e+02 3.102e+01 (TITAN V) 4096 4096 4096 2.060e-02 6.674e+03 2.606e+01 100 4.306e+00 2.090e+02 3.193e+01 (TITAN V) 4608 4608 4608 3.070e-02 6.376e+03 2.213e+01 100 6.260e+00 2.039e+02 3.127e+01 (TITAN V) 5120 5120 5120 4.322e-02 6.212e+03 1.941e+01 100 8.002e+00 1.851e+02 3.355e+01 (TITAN V) 5632 5632 5632 5.990e-02 5.966e+03 1.695e+01 100 1.085e+01 1.811e+02 3.294e+01 (TITAN V) 6144 6144 6144 7.563e-02 6.135e+03 1.597e+01 100 1.417e+01 1.873e+02 3.275e+01 (TITAN V) 6656 6656 6656 9.592e-02 6.150e+03 1.478e+01 100 1.816e+01 1.893e+02 3.249e+01 (TITAN V) 7168 7168 7168 1.207e-01 6.103e+03 1.362e+01 100 2.299e+01 1.904e+02 3.204e+01 (TITAN V) 7680 7680 7680 1.455e-01 6.228e+03 1.297e+01 100 2.826e+01 1.942e+02 3.207e+01 (TITAN V) 8192 8192 8192 1.778e-01 6.185e+03 1.208e+01 100 3.480e+01 1.957e+02 3.161e+01 (TITAN V) blas_dot2_v01a/eval_jcam2019/_testing_cublas_dcsrmv_check.dat000644 000765 000024 00000003641 13532503470 025400 0ustar00mukunokistaff000000 000000 # % Reading sparse matrix from file (/home/mukunoki/matrix/cage15.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/cage15.mtx 5154859 5154859 99199551 ### condmax = 5.755e+01 4.893095e-16 1869613 % Reading sparse matrix from file (/home/mukunoki/matrix/crankseg_1.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/crankseg_1.mtx 52804 52804 10614210 ### condmax = 3.939e+08 6.384894e-10 37996 % Reading sparse matrix from file (/home/mukunoki/matrix/dielFilterV3real.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/dielFilterV3real.mtx 1102824 1102824 89306020 ### condmax = 4.948e+08 8.493910e-10 774210 % Reading sparse matrix from file (/home/mukunoki/matrix/laminar_duct3D.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/laminar_duct3D.mtx 67173 67173 3788857 ### condmax = 3.869e+05 4.358652e-12 42606 % Reading sparse matrix from file (/home/mukunoki/matrix/lhr71.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/lhr71.mtx 70304 70304 1494006 ### condmax = 4.639e+05 1.129422e-12 14471 % Reading sparse matrix from file (/home/mukunoki/matrix/nd24k.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/nd24k.mtx 72000 72000 28715634 ### condmax = 1.652e+06 1.091629e-11 59412 % Reading sparse matrix from file (/home/mukunoki/matrix/pdb1HYS.mtx): done. Converting to CSR: % Detected symmetric case. done. /home/mukunoki/matrix/pdb1HYS.mtx 36417 36417 4344765 ### condmax = 7.362e+05 1.023168e-12 27112 % Reading sparse matrix from file (/home/mukunoki/matrix/venkat25.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/venkat25.mtx 62424 62424 1717763 ### condmax = 1.685e+06 4.226907e-12 42701 % Reading sparse matrix from file (/home/mukunoki/matrix/xenon1.mtx): done. Converting to CSR: done. /home/mukunoki/matrix/xenon1.mtx 48600 48600 1181120 ### condmax = 2.035e+05 2.832868e-12 34305 blas_dot2_v01a/testing/prec_sx.h000644 000765 000024 00000011144 13531160667 020065 0ustar00mukunokistaff000000 000000 #ifndef PREC_SX_H #define PREC_SX_H #ifdef PREC_SX #define FPADDCOUNT 1 #define FPMULCOUNT 1 #define FPMADCOUNT 2 // TYPE #define CUBLAS_TYPE float #define CUBLAS_BASETYPE CUBLAS_TYPE #define CUBLAS_ZERO 0. #define CUBLAS_ONE 1. #define CUBLAS_NEGONE -1. #define CBLAS_TYPE float #define CBLAS_BASETYPE CBLAS_TYPE #define CBLAS_ZERO 0. #define CBLAS_ONE 1. #define CBLAS_NEGONE -1. #define MBLASQD_TYPE qd_real #define MBLASQD_BASETYPE MBLASQD_TYPE #define MBLASQD_ZERO qd_real(0.) #define MBLASQD_ONE qd_real(1.) #define MBLASQD_NEGONE qd_real(-1.) #define MBLASMPFR_TYPE mpreal #define MBLASMPFR_BASETYPE MBLASMPFR_TYPE #define MBLASMPFR_ZERO 0. #define MBLASMPFR_ONE 1. #define MBLASMPFR_NEGONE -1. #if defined (MUBLAS) #define GPU_TYPE float #elif defined (CUBLAS) #define GPU_TYPE float #elif defined (KBLAS) #define GPU_TYPE float #elif defined (MAGMA) #define GPU_TYPE float #elif defined (CULA) #define GPU_TYPE float #elif defined (ASPEN) #define GPU_TYPE float #endif #define MAKE_GPU_TYPE(x) (x) #define GPU_TYPE_TO_DOUBLE(x) (x) //#define MAKE_GPU_TYPE_REAL(r) (r) // COPY #define CBLAS_COPY cblas_scopy #define MBLASQD_COPY Rcopy #define MBLASMPFR_COPY Rcopy #define MUBLAS_COPY mublasSXcopy #define CUBLAS_COPY cublasScopy #define MAGMA_COPY magmablas_scopy #define CULA_COPY culaDeviceScopy #define KBLAS_COPY kblas_scopy // SCAL #define CBLAS_SCAL cblas_sscal #define MBLASQD_SCAL Rscal #define MBLASMPFR_SCAL Rscal #define MUBLAS_SCAL mublasSXscal #define CUBLAS_SCAL cublasSscal #define MAGMA_SCAL #define CULA_SCAL #define KBLAS_SCAL // AXPY #define CBLAS_AXPY cblas_saxpy #define MBLASQD_AXPY Raxpy #define MBLASMPFR_AXPY Raxpy #define MUBLAS_AXPY mublasSXaxpy #define CUBLAS_AXPY cublasSaxpy #define MAGMA_AXPY magmablas_saxpy #define CULA_AXPY culaDeviceSaxpy #define KBLAS_AXPY kblas_saxpy // DOT #define CBLAS_DOT cblas_sdot #define MBLASQD_DOT Rdot #define MBLASMPFR_DOT Rdot #define MUBLAS_DOT mublasSXdot #define CUBLAS_DOT cublasSdot #define MAGMA_DOT magmablas_sdot #define CULA_DOT culaDeviceSdot #define KBLAS_DOT kblas_sdot // ASUM #define CBLAS_ASUM cblas_sasum #define MBLASQD_ASUM Rasum #define MBLASMPFR_ASUM Rasum #define MUBLAS_ASUM mublasSXasum #define CUBLAS_ASUM cublasSasum #define MAGMA_ASUM magmablas_sasum #define CULA_ASUM culaDeviceSasum #define KBLAS_ASUM kblas_sasum // GEMV #define MUBLAS_GEMV_MGPU_ASYNC mublasSXgemvMgpuAsync #define MUBLAS_GEMV_MGPU mublasSXgemvMgpu #define CBLAS_GEMV cblas_sgemv #define MBLASQD_GEMV Rgemv #define MBLASMPFR_GEMV Rgemv #define MUBLAS_GEMV mublasSXgemv #define CUBLAS_GEMV cublasSgemv #define MAGMA_GEMV magmablas_sgemv #define CULA_GEMV culaDeviceSgemv #define KBLAS_GEMV kblas_sgemv #define ASPEN_GEMV ASPEN_sgemv // SYMV #define CBLAS_SYMV cblas_ssymv #define MBLASQD_SYMV Rsymv #define MBLASMPFR_SYMV Rsymv #define MUBLAS_SYMV mublasSXsymv #define CUBLAS_SYMV cublasSsymv #define MAGMA_SYMV magmablas_ssymv #define CULA_SYMV culaDeviceSsymv #define KBLAS_SYMV kblas_ssymv #define ASPEN_SYMV ASPEN_ssymv // TRMV #define CBLAS_TRMV cblas_strmv #define MBLASQD_TRMV Rtrmv #define MBLASMPFR_TRMV Rtrmv #define MUBLAS_TRMV mublasSXtrmv #define CUBLAS_TRMV cublasStrmv #define MAGMA_TRMV magmablas_strmv #define CULA_TRMV culaDeviceStrmv #define KBLAS_TRMV #define ASPEN_TRMV // TRSV #define CBLAS_TRSV cblas_strsv #define MBLASQD_TRSV Rtrsv #define MBLASMPFR_TRSV Rtrsv #define MUBLAS_TRSV mublasSXtrsv #define CUBLAS_TRSV cublasStrsv #define MAGMA_TRSV magmablas_strsv #define CULA_TRSV culaDeviceStrsv #define KBLAS_TRSV #define ASPEN_TRSV // GEMM #define BLASX_GEMM blasx_sgemm #define CBLAS_GEMM cblas_sgemm #define MBLASQD_GEMM Rgemm #define MBLASMPFR_GEMM Rgemm #define MUBLAS_GEMM mublasSXgemm #define CUBLAS_GEMM cublasSgemm #define CUBLAS_GEMM_MGPU cublasXtSgemm #define CUBLAS_GEMM_BATCHED cublasSgemmBatched #define MAGMA_GEMM magmablas_sgemm #define CULA_GEMM culaDeviceSgemm #define KBLAS_GEMM #define ASPEN_GEMM // IA_GEMM #define MUBLAS_IA_GEMM_PP mublasIASgemmPP #define MUBLAS_IA_GEMM_II mublasIASgemmII #define MUBLAS_IA_GEMM_II_b mublasIASgemmII_b // NRM2 #define CUBLAS_NRM cublasSnrm2 #define CBLAS_NRM cblas_snrm2 #define MBLASQD_NRM Rnrm2 #define MBLASMPFR_NRM Rnrm2 // GER #define CBLAS_GER cblas_sger #define MBLASQD_GER Rger #define MBLASMPFR_GER Rger #define MUBLAS_GER #define CUBLAS_GER cublasSger #define MAGMA_GER magmablas_sger #define CULA_GER culaDeviceSger #define KBLAS_GER #define ASPEN_GER // CSRMV #define MUBLAS_CSRMV mublasSXcsrmv #define CUBLAS_CSRMV cusparseScsrmv // HYBMV #define CUBLAS_HYBMV cusparseShybmv #define SPARSE_FORMAT_CONVERT_FROM_SCR cusparseScsr2hyb // GEAM #define MUBLAS_GEAM mublasSXgeam #define CUBLAS_GEAM cublasSgeam #endif #endif blas_dot2_v01a/testing/testing_level2s.cpp000644 000765 000024 00000016006 13531415173 022063 0ustar00mukunokistaff000000 000000 #include #include #include #define ROUTINE_FLOPS(m,n,k) (2*k+2*m+m) #define ROUTINE_BYTES(m,n,k,s) ((k+2*m+n)*s+(k+m+1)*4) #include "testing_common.h" #include "testing_common.cpp" #if defined (MUBLAS) #define ROUTINE_TARGET(ha,th,m,n,nnz,al,dscA,Aval,Aptr,Aind,X,bt,Y) MUBLAS_CSRMV(&ha,th.tranA,m,n,nnz,&al,Aval,Aptr,Aind,X,&bt,Y) #elif defined (CUBLAS) #define ROUTINE_TARGET(ha,th,m,n,nnz,al,dscA,Aval,Aptr,Aind,X,bt,Y) CUBLAS_CSRMV(ha,cusparse_trans_const_m(th.tranA),m,n,nnz,&al,dscA,Aval,Aptr,Aind,X,&bt,Y) #endif void mpfrCsrmv ( testingHandle_t th, int32_t m, int32_t n, int32_t nnz, mpreal alpha, mpreal* matA, int32_t* matAptr, int32_t* matAind, mpreal* x, mpreal beta, mpreal* y ) { int i, j; mpreal t; for(j = 0; j < m; j++) { t = 0.; for(i = matAptr[j]; i < matAptr[j+1]; i++) t = t + matA[i] * x[matAind[i]]; y[j] = alpha * t + beta * y[j]; } } double mpfrCsrmvCond ( testingHandle_t th, int32_t m, int32_t n, int32_t nnz, mpreal* matA, int32_t* matAptr, int32_t* matAind, mpreal* x ) { // cond (xTy) := 2|xT||y|/|xTy|, xTy neq 0 int i, j; mpreal y, t, s; mpreal condmax = 0.; mpreal nrmAi, nrmX, condi; for(j = 0; j < m; j++) { y = 0.; // nrmA & nrmX nrmAi = 0.; nrmX = 0.; for(i = matAptr[j]; i < matAptr[j+1]; i++) { t = matA[i]; nrmAi += t*t; s = x[matAind[i]]; nrmX += s*s; } nrmAi = sqrt(nrmAi); nrmX = sqrt(nrmX); // y = Ax for(i = matAptr[j]; i < matAptr[j+1]; i++) y = y + matA[i] * x[matAind[i]]; condi = 2.*nrmAi*nrmX/y; if (condi > condmax) condmax = condi; } return mpfr_get_d(condmax,MPFR_RNDN); } int32_t main (int32_t argc, char **argv) { size_t i; double t0, t1; mpfr_set_default_prec(MPFR_PREC); mpreal::set_default_prec(MPFR_PREC); // testing setup ------------------------------ testingHandle_t th; testingCreate (argc, argv, &th); print_info1 (&th); // -------------------------------------------- // library setup ------------------------------ unsigned long long energy0, energy1; nvmlDevice_t nvmldev; nvmlInit(); nvmlDeviceGetHandleByIndex(1, &nvmldev); char devname[256]; nvmlDeviceGetName(nvmldev, devname, 256); cusparseMatDescr_t descrA; cusparseCreateMatDescr (&descrA); cusparseSetMatType (descrA, CUSPARSE_MATRIX_TYPE_GENERAL); cusparseSetMatIndexBase (descrA, CUSPARSE_INDEX_BASE_ZERO); magma_init(); #if defined (MUBLAS) mublasHandle_t ha; mublasCreate (&ha); set_mublas_handler (&th, &ha); #elif defined (CUBLAS) cusparseHandle_t ha; cusparseCreate (&ha); // cusparsePointerMode(ha, CUSPARSE_POINTER_MODE_VALUE); #endif // -------------------------------------------- // memory setup ------------------------------- magma_queue_t queue = NULL; magma_queue_create (0, &queue); #if defined (PREC_S) || (PREC_SX) magma_s_matrix hst_A={Magma_CSR}, dev_A={Magma_CSR}; magma_s_csr_mtx (&hst_A, th.mtx_file, queue); #elif defined (PREC_D) || (PREC_DX) magma_d_matrix hst_A={Magma_CSR}, dev_A={Magma_CSR}; magma_d_csr_mtx (&hst_A, th.mtx_file, queue); #endif th.dim_m_dev = hst_A.num_rows; th.dim_n_dev = hst_A.num_cols; th.dim_k_dev = hst_A.nnz; // malloc host memory GPU_TYPE alpha, beta; GPU_TYPE *hst_X = new GPU_TYPE[hst_A.num_cols]; GPU_TYPE *hst_Y = new GPU_TYPE[hst_A.num_rows]; GPU_TYPE *hst_Y_t = new GPU_TYPE[hst_A.num_rows]; // initialize mublasInitMat (1, 1, 0, &alpha, 1.); mublasInitMat (1, 1, 0, &beta, 0.); mublasInitMatRand (hst_A.num_cols, 1, 0, hst_X); mublasInitMat (hst_A.num_rows, 1, 0, hst_Y, 0.); // -------------------------------------------- print_info2 (&th); // evaluation --------------------------------- GPU_TYPE *dev_X, *dev_Y; cudaMalloc ((void **) &dev_X, sizeof (GPU_TYPE) * hst_A.num_cols); cudaMalloc ((void **) &dev_Y, sizeof (GPU_TYPE) * hst_A.num_rows); #if defined (PREC_S) || (PREC_SX) magma_smtransfer (hst_A, &dev_A, Magma_CPU, Magma_DEV, queue); #elif defined (PREC_D) || (PREC_DX) magma_dmtransfer (hst_A, &dev_A, Magma_CPU, Magma_DEV, queue); #endif cublasSetVector (hst_A.num_cols, sizeof(GPU_TYPE), hst_X, 1, dev_X, 1); cublasSetVector (hst_A.num_rows, sizeof(GPU_TYPE), hst_Y, 1, dev_Y, 1); printf ("%s\t%zd\t%zd\t%zd\t", th.mtx_file, (size_t)hst_A.num_rows, (size_t)hst_A.num_cols, (size_t)hst_A.nnz); get_routine_theoretial_performance (&th); // execution --------------------------------- if (th.mode == 'p') { // warm up for (i = 0; i < WarmUpLoop; i++) ROUTINE_TARGET(ha,th,hst_A.num_rows,hst_A.num_cols,hst_A.nnz,alpha,descrA,dev_A.dval,dev_A.drow,dev_A.dcol,dev_X,beta,dev_Y); nvmlDeviceGetTotalEnergyConsumption (nvmldev, &energy0); t0 = gettime (); for (i = 0; i < th.iter; i++) ROUTINE_TARGET(ha,th,hst_A.num_rows,hst_A.num_cols,hst_A.nnz,alpha,descrA,dev_A.dval,dev_A.drow,dev_A.dcol,dev_X,beta,dev_Y); t1 = gettime (); nvmlDeviceGetTotalEnergyConsumption (nvmldev, &energy1); double sec = (t1 - t0) / (double)th.iter; double joules = (energy1 - energy0)*1.e-3 / (double)th.iter; double watt = joules / sec; double gfpw = (th.routine_flops) * 1.0e-9 / joules; printf ("\t%1.3e\t%1.3e\t%1.3e\t%zd", sec, (th.routine_flops / sec) * 1.0e-9, (th.routine_bytes / sec) * 1.0e-9, (size_t)th.iter); printf ("\t%1.3e\t%1.3e\t%1.3e\t(%s)", joules, watt, gfpw, devname); } if (th.mode == 'c') { ROUTINE_TARGET(ha,th,hst_A.num_rows,hst_A.num_cols,hst_A.nnz,alpha,descrA,dev_A.dval,dev_A.drow,dev_A.dcol,dev_X,beta,dev_Y); } // ------------------------------------------- if (th.mode == 'c') cublasGetVector (hst_A.num_rows, sizeof(GPU_TYPE), dev_Y, 1, hst_Y_t, 1); cudaFree (dev_X); cudaFree (dev_Y); if (th.mode == 'c') { mpreal alpha_r = 0; mpreal beta_r = 0; mpreal *hst_A_r = new mpreal[hst_A.nnz]; mpreal *hst_X_r = new mpreal[hst_A.num_cols]; mpreal *hst_Y_r = new mpreal[hst_A.num_rows]; mublasConvert2D (1, 1, 0, &alpha, &alpha_r); mublasConvert2D (1, 1, 0, &beta, &beta_r); mublasConvert2D (hst_A.nnz, 1, 0, hst_A.dval, hst_A_r); mublasConvert2D (hst_A.num_cols, 1, 0, hst_X, hst_X_r); mublasConvert2D (hst_A.num_rows, 1, 0, hst_Y, hst_Y_r); mpfrCsrmv (th,hst_A.num_rows, hst_A.num_cols, hst_A.nnz, alpha_r, hst_A_r, hst_A.drow, hst_A.dcol, hst_X_r, beta_r, hst_Y_r); double condmax; condmax = mpfrCsrmvCond (th,hst_A.num_rows, hst_A.num_cols, hst_A.nnz, hst_A_r, hst_A.drow, hst_A.dcol, hst_X_r); printf ("### condmax = %1.3e\n", condmax); mublasCheckMatrix (hst_A.num_rows, 1, hst_Y_t, hst_A.num_rows, hst_Y_r, hst_A.num_rows); delete[]hst_A_r; delete[]hst_X_r; delete[]hst_Y_r; } printf ("\n"); // -------------------------------------------- // shutdown ----------------------------------- #if defined (PREC_S) || (PREC_SX) magma_smfree (&hst_A, queue); magma_smfree (&dev_A, queue); #elif defined (PREC_D) || (PREC_DX) magma_dmfree (&hst_A, queue); magma_dmfree (&dev_A, queue); #endif magma_queue_destroy (queue); magma_finalize (); delete[]hst_X; delete[]hst_Y; delete[]hst_Y_t; #if defined (MUBLAS) mublasDestroy (&ha); #elif defined (CUBLAS) cusparseDestroy (ha); #endif nvmlShutdown (); // -------------------------------------------- return 0; } blas_dot2_v01a/testing/prec_s.h000644 000765 000024 00000011123 13531160667 017672 0ustar00mukunokistaff000000 000000 #ifndef PREC_S_H #define PREC_S_H #ifdef PREC_S #define FPADDCOUNT 1 #define FPMULCOUNT 1 #define FPMADCOUNT 2 // TYPE #define CUBLAS_TYPE float #define CUBLAS_BASETYPE CUBLAS_TYPE #define CUBLAS_ZERO 0. #define CUBLAS_ONE 1. #define CUBLAS_NEGONE -1. #define CBLAS_TYPE float #define CBLAS_BASETYPE CBLAS_TYPE #define CBLAS_ZERO 0. #define CBLAS_ONE 1. #define CBLAS_NEGONE -1. #define MBLASQD_TYPE qd_real #define MBLASQD_BASETYPE MBLASQD_TYPE #define MBLASQD_ZERO qd_real(0.) #define MBLASQD_ONE qd_real(1.) #define MBLASQD_NEGONE qd_real(-1.) #define MBLASMPFR_TYPE mpreal #define MBLASMPFR_BASETYPE MBLASMPFR_TYPE #define MBLASMPFR_ZERO 0. #define MBLASMPFR_ONE 1. #define MBLASMPFR_NEGONE -1. #if defined (MUBLAS) #define GPU_TYPE float #elif defined (CUBLAS) #define GPU_TYPE float #elif defined (KBLAS) #define GPU_TYPE float #elif defined (MAGMA) #define GPU_TYPE float #elif defined (CULA) #define GPU_TYPE float #elif defined (ASPEN) #define GPU_TYPE float #endif #define MAKE_GPU_TYPE(x) (x) #define GPU_TYPE_TO_DOUBLE(x) (x) //#define MAKE_GPU_TYPE_REAL(r) (r) // COPY #define CBLAS_COPY cblas_scopy #define MBLASQD_COPY Rcopy #define MBLASMPFR_COPY Rcopy #define MUBLAS_COPY mublasScopy #define CUBLAS_COPY cublasScopy #define MAGMA_COPY magmablas_scopy #define CULA_COPY culaDeviceScopy #define KBLAS_COPY kblas_scopy // SCAL #define CBLAS_SCAL cblas_sscal #define MBLASQD_SCAL Rscal #define MBLASMPFR_SCAL Rscal #define MUBLAS_SCAL mublasSscal #define CUBLAS_SCAL cublasSscal #define MAGMA_SCAL #define CULA_SCAL #define KBLAS_SCAL // AXPY #define CBLAS_AXPY cblas_saxpy #define MBLASQD_AXPY Raxpy #define MBLASMPFR_AXPY Raxpy #define MUBLAS_AXPY mublasSaxpy #define CUBLAS_AXPY cublasSaxpy #define MAGMA_AXPY magmablas_saxpy #define CULA_AXPY culaDeviceSaxpy #define KBLAS_AXPY kblas_saxpy // DOT #define CBLAS_DOT cblas_sdot #define MBLASQD_DOT Rdot #define MBLASMPFR_DOT Rdot #define MUBLAS_DOT mublasSdot #define CUBLAS_DOT cublasSdot #define MAGMA_DOT magmablas_sdot #define CULA_DOT culaDeviceSdot #define KBLAS_DOT kblas_sdot // ASUM #define CBLAS_ASUM cblas_sasum #define MBLASQD_ASUM Rasum #define MBLASMPFR_ASUM Rasum #define MUBLAS_ASUM mublasSasum #define CUBLAS_ASUM cublasSasum #define MAGMA_ASUM magmablas_sasum #define CULA_ASUM culaDeviceSasum #define KBLAS_ASUM kblas_sasum // GEMV #define MUBLAS_GEMV_MGPU_ASYNC mublasSgemvMgpuAsync #define MUBLAS_GEMV_MGPU mublasSgemvMgpu #define CBLAS_GEMV cblas_sgemv #define MBLASQD_GEMV Rgemv #define MBLASMPFR_GEMV Rgemv #define MUBLAS_GEMV mublasSgemv #define CUBLAS_GEMV cublasSgemv #define MAGMA_GEMV magmablas_sgemv #define CULA_GEMV culaDeviceSgemv #define KBLAS_GEMV kblas_sgemv #define ASPEN_GEMV ASPEN_sgemv // SYMV #define CBLAS_SYMV cblas_ssymv #define MBLASQD_SYMV Rsymv #define MBLASMPFR_SYMV Rsymv #define MUBLAS_SYMV mublasSsymv #define CUBLAS_SYMV cublasSsymv #define MAGMA_SYMV magmablas_ssymv #define CULA_SYMV culaDeviceSsymv #define KBLAS_SYMV kblas_ssymv #define ASPEN_SYMV ASPEN_ssymv // TRMV #define CBLAS_TRMV cblas_strmv #define MBLASQD_TRMV Rtrmv #define MBLASMPFR_TRMV Rtrmv #define MUBLAS_TRMV mublasStrmv #define CUBLAS_TRMV cublasStrmv #define MAGMA_TRMV magmablas_strmv #define CULA_TRMV culaDeviceStrmv #define KBLAS_TRMV #define ASPEN_TRMV // TRSV #define CBLAS_TRSV cblas_strsv #define MBLASQD_TRSV Rtrsv #define MBLASMPFR_TRSV Rtrsv #define MUBLAS_TRSV mublasStrsv #define CUBLAS_TRSV cublasStrsv #define MAGMA_TRSV magmablas_strsv #define CULA_TRSV culaDeviceStrsv #define KBLAS_TRSV #define ASPEN_TRSV // GEMM #define BLASX_GEMM blasx_sgemm #define CBLAS_GEMM cblas_sgemm #define MBLASQD_GEMM Rgemm #define MBLASMPFR_GEMM Rgemm #define MUBLAS_GEMM mublasSgemm #define CUBLAS_GEMM cublasSgemm #define CUBLAS_GEMM_MGPU cublasXtSgemm #define CUBLAS_GEMM_BATCHED cublasSgemmBatched #define MAGMA_GEMM magmablas_sgemm #define CULA_GEMM culaDeviceSgemm #define KBLAS_GEMM #define ASPEN_GEMM // IA_GEMM #define MUBLAS_IA_GEMM_PP mublasIASgemmPP #define MUBLAS_IA_GEMM_II mublasIASgemmII #define MUBLAS_IA_GEMM_II_b mublasIASgemmII_b // NRM2 #define CUBLAS_NRM cublasSnrm2 #define CBLAS_NRM cblas_snrm2 #define MBLASQD_NRM Rnrm2 #define MBLASMPFR_NRM Rnrm2 // GER #define CBLAS_GER cblas_sger #define MBLASQD_GER Rger #define MBLASMPFR_GER Rger #define MUBLAS_GER #define CUBLAS_GER cublasSger #define MAGMA_GER magmablas_sger #define CULA_GER culaDeviceSger #define KBLAS_GER #define ASPEN_GER // CSRMV #define MUBLAS_CSRMV mublasScsrmv #define CUBLAS_CSRMV cusparseScsrmv // HYBMV #define CUBLAS_HYBMV cusparseShybmv #define SPARSE_FORMAT_CONVERT_FROM_SCR cusparseScsr2hyb // GEAM #define MUBLAS_GEAM mublasSgeam #define CUBLAS_GEAM cublasSgeam #endif #endif blas_dot2_v01a/testing/Makefile000644 000765 000024 00000017065 13531665133 017717 0ustar00mukunokistaff000000 000000 # Makefile include ../make.inc ############################################## #--- Lib ------------------------------------- TESTING_CUBLAS = yes TESTING_MUBLAS = yes #--- reference blas -------------------------- CHECK_CUBLAS = no CHECK_MBLASQD = no CHECK_MBLASMPFR = yes #--- Setting --------------------------------- USE_NVML = yes ############################################## #--- PATH ------------------------------------ MUBLAS_DIR = .. MUBLAS_LDFLAGS = -L$(MUBLAS_DIR)/lib MUBLAS_INC = -I$(MUBLAS_DIR)/include CUDA_LIBS = -lcuda -lcudart -lcublas -lcusparse #--- Optional -------------------------------- BLAS_LDFLAGS = -L$(HOME)/etc/BLAS/lib BLAS_LIBS = -lblas F2C_INC = -I$(HOME)/etc/f2c MPACK_DIR = $(HOME)/local MPACK_LDFLAGS = -L$(MPACK_DIR)/lib MPACK_INC = -I$(MPACK_DIR)/include/mpack QD_DIR = $(HOME)/etc/mpack-0.8.0/external/qd/work/install/qd-2.3.7 QD_LDFLAGS = -L$(QD_DIR)/src QD_INC = -I$(QD_DIR)/include MPFR_DIR = $(HOME)/local MPFR_LDFLAGS = -L$(MPFR_DIR)/lib MPFR_INC = -I$(MPFR_DIR)/include MAGMA_DIR = $(HOME)/local/magma MAGMA_LDFLAGS = -L$(MAGMA_DIR)/lib MAGMA_INC = -I$(MAGMA_DIR)/include MAGMA_LIBS = -lmagma -lmagma_sparse -DMAGMA_WITH_MKL -DMKL_ILP64 -pedantic -Wno-long-long ############################################## # -------------------------------------------- # common ------------------------------------- CXX = icc IXX = icc FLAGS = -O3 -Wall -MD -fno-strict-aliasing LDFLAGS = $(CUDA_LDFLAGS) -L$(HOME)/local/lib LIBS = $(CUDA_LIBS) -lm -lstdc++ ifeq ($(USE_NVML),yes) FLAGS += -DUSE_NVML LIBS += -lnvidia-ml #-lgsl -lgslcblas endif INCS += $(CUDA_INC) -I$(HOME)/local/include # DOT --------------------------------------- ifeq ($(DOT),yes) ifeq ($(PREC_S),yes) CUBLAS_OBJS += testing_cublas_sdot MUBLAS_OBJS += testing_mublas_sdot endif ifeq ($(PREC_D),yes) CUBLAS_OBJS += testing_cublas_ddot MUBLAS_OBJS += testing_mublas_ddot endif ifeq ($(PREC_SX),yes) MUBLAS_OBJS += testing_mublas_sxdot endif ifeq ($(PREC_DX),yes) MUBLAS_OBJS += testing_mublas_dxdot endif endif # GEMV --------------------------------------- ifeq ($(GEMV),yes) ifeq ($(PREC_S),yes) CUBLAS_OBJS += testing_cublas_sgemv MUBLAS_OBJS += testing_mublas_sgemv endif ifeq ($(PREC_D),yes) CUBLAS_OBJS += testing_cublas_dgemv MUBLAS_OBJS += testing_mublas_dgemv endif ifeq ($(PREC_SX),yes) MUBLAS_OBJS += testing_mublas_sxgemv endif ifeq ($(PREC_DX),yes) MUBLAS_OBJS += testing_mublas_dxgemv endif endif # CSRMV --------------------------------------- ifeq ($(CSRMV),yes) ifeq ($(PREC_S),yes) CUBLAS_OBJS += testing_cublas_scsrmv MUBLAS_OBJS += testing_mublas_scsrmv endif ifeq ($(PREC_D),yes) CUBLAS_OBJS += testing_cublas_dcsrmv MUBLAS_OBJS += testing_mublas_dcsrmv endif ifeq ($(PREC_SX),yes) MUBLAS_OBJS += testing_mublas_sxcsrmv endif ifeq ($(PREC_DX),yes) MUBLAS_OBJS += testing_mublas_dxcsrmv endif endif # GEMM --------------------------------------- ifeq ($(GEMM),yes) ifeq ($(PREC_S),yes) CUBLAS_OBJS += testing_cublas_sgemm MUBLAS_OBJS += testing_mublas_sgemm endif ifeq ($(PREC_D),yes) CUBLAS_OBJS += testing_cublas_dgemm MUBLAS_OBJS += testing_mublas_dgemm endif ifeq ($(PREC_SX),yes) MUBLAS_OBJS += testing_mublas_sxgemm endif ifeq ($(PREC_DX),yes) MUBLAS_OBJS += testing_mublas_dxgemm endif endif ifeq ($(CHECK_MBLASQD),yes) FLAGS += -DCHECK_MBLASQD INCS += $(QD_INC) $(MPACK_INC) LDFLAGS += $(QD_LDFLAGS) $(MPACK_LDFLAGS) LIBS += -lmblas_qd -lqd -fopenmp endif ifeq ($(CHECK_MBLASMPFR),yes) FLAGS += -DCHECK_MBLASMPFR INCS += $(MPFR_INC) $(MPACK_INC) LDFLAGS += $(MPFR_LDFLAGS) $(MPACK_LDFLAGS) LIBS += -lmblas_mpfr -lmpfr -fopenmp -lmpfrcxx -L$(MPACK_DIR)/external/i/MPC/lib/ -L$(MPACK_DIR)/external/i/MPFR/lib/ -L$(MPACK_DIR)/external/i/GMP/lib/ -lmpfr -lmpc -lgmp endif ifeq ($(CHECK_CUBLAS),yes) FLAGS += -DCHECK_CUBLAS endif ifeq ($(TESTING_CUBLAS),yes) OBJS += $(CUBLAS_OBJS) endif ifeq ($(TESTING_MUBLAS),yes) OBJS += $(MUBLAS_OBJS) INCS += $(MUBLAS_INC) LDFLAGS += $(MUBLAS_LDFLAGS) LIBS += -lmublas endif default: $(OBJS) SRC_DEV = testing_devinfo.cpp SRC_NVML= testing_nvml.cpp SRC_L1 = testing_level1.cpp SRC_L1B = testing_level1b.cpp SRC_L2 = testing_level2.cpp SRC_L2S = testing_level2s.cpp SRC_L3 = testing_level3.cpp # -------------------------------------------- ### MUBLAS ################################################################################################### testing_mublas_devinfo: $(SRC_DEV) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DAXPY -DMUBLAS -DPREC_S testing_nvml: $(SRC_NVML) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) testing_mublas_sdot: $(SRC_L1B) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DDOT -DMUBLAS -DPREC_S testing_mublas_ddot: $(SRC_L1B) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DDOT -DMUBLAS -DPREC_D testing_mublas_sxdot: $(SRC_L1B) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DDOT -DMUBLAS -DPREC_SX testing_mublas_dxdot: $(SRC_L1B) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DDOT -DMUBLAS -DPREC_DX testing_mublas_sgemv: $(SRC_L2) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMV -DMUBLAS -DPREC_S testing_mublas_dgemv: $(SRC_L2) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMV -DMUBLAS -DPREC_D testing_mublas_sxgemv: $(SRC_L2) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMV -DMUBLAS -DPREC_SX testing_mublas_dxgemv: $(SRC_L2) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMV -DMUBLAS -DPREC_DX testing_mublas_scsrmv: $(SRC_L2S) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DCSRMV -DMUBLAS -DPREC_S $(MAGMA_INC) $(MAGMA_LDFLAGS) $(MAGMA_LIBS) testing_mublas_dcsrmv: $(SRC_L2S) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DCSRMV -DMUBLAS -DPREC_D $(MAGMA_INC) $(MAGMA_LDFLAGS) $(MAGMA_LIBS) testing_mublas_sxcsrmv: $(SRC_L2S) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DCSRMV -DMUBLAS -DPREC_SX $(MAGMA_INC) $(MAGMA_LDFLAGS) $(MAGMA_LIBS) testing_mublas_dxcsrmv: $(SRC_L2S) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DCSRMV -DMUBLAS -DPREC_DX $(MAGMA_INC) $(MAGMA_LDFLAGS) $(MAGMA_LIBS) testing_mublas_sgemm: $(SRC_L3) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMM -DMUBLAS -DPREC_S testing_mublas_dgemm: $(SRC_L3) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMM -DMUBLAS -DPREC_D testing_mublas_sxgemm: $(SRC_L3) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMM -DMUBLAS -DPREC_SX testing_mublas_dxgemm: $(SRC_L3) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMM -DMUBLAS -DPREC_DX ### CUBLAS ################################################################################################### testing_cublas_sdot: $(SRC_L1B) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DDOT -DCUBLAS -DPREC_S testing_cublas_ddot: $(SRC_L1B) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DDOT -DCUBLAS -DPREC_D testing_cublas_sgemv: $(SRC_L2) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMV -DCUBLAS -DPREC_S testing_cublas_dgemv: $(SRC_L2) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMV -DCUBLAS -DPREC_D testing_cublas_scsrmv: $(SRC_L2S) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DCSRMV -DCUBLAS -DPREC_S $(MAGMA_INC) $(MAGMA_LDFLAGS) $(MAGMA_LIBS) testing_cublas_dcsrmv: $(SRC_L2S) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DCSRMV -DCUBLAS -DPREC_D $(MAGMA_INC) $(MAGMA_LDFLAGS) $(MAGMA_LIBS) testing_cublas_sgemm: $(SRC_L3) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMM -DCUBLAS -DPREC_S testing_cublas_dgemm: $(SRC_L3) $(CXX) $< -o $@ $(FLAGS) $(INCS) $(LDFLAGS) $(LIBS) -DGEMM -DCUBLAS -DPREC_D clean: $(RM) $(OBJS) $(RM) *.d -include *.d .PHONY: all clean blas_dot2_v01a/testing/testing_common.h000644 000765 000024 00000001426 13531166236 021447 0ustar00mukunokistaff000000 000000 #ifndef TESTING_COMMON #define TESTING_COMMON // header ------------------------------------------ #if defined (MUBLAS) #include #endif #include "testing_setting.h" #include #include #include #include #include #define __STDC_FORMAT_MACROS #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined (PREC_S) #include "prec_s.h" #endif #if defined (PREC_D) #include "prec_d.h" #endif #if defined (PREC_SX) #include "prec_sx.h" #endif #if defined (PREC_DX) #include "prec_dx.h" #endif #endif blas_dot2_v01a/testing/prec_dx.h000644 000765 000024 00000010212 13531160667 020041 0ustar00mukunokistaff000000 000000 #ifndef PREC_DX_H #define PREC_DX_H #ifdef PREC_DX #define FPADDCOUNT 1 #define FPMULCOUNT 1 #define FPMADCOUNT 2 // TYPE #define CUBLAS_TYPE double #define CUBLAS_BASETYPE CUBLAS_TYPE #define CUBLAS_ZERO 0. #define CUBLAS_ONE 1. #define CUBLAS_NEGONE -1. #define CBLAS_TYPE double #define CBLAS_BASETYPE CBLAS_TYPE #define CBLAS_ZERO 0. #define CBLAS_ONE 1. #define CBLAS_NEGONE -1. #define MBLASQD_TYPE qd_real #define MBLASQD_BASETYPE MBLASQD_TYPE #define MBLASQD_ZERO qd_real(0.) #define MBLASQD_ONE qd_real(1.) #define MBLASQD_NEGONE qd_real(-1.) #define MBLASMPFR_TYPE mpreal #define MBLASMPFR_BASETYPE MBLASMPFR_TYPE #define MBLASMPFR_ZERO 0. #define MBLASMPFR_ONE 1. #define MBLASMPFR_NEGONE -1. #if defined (MUBLAS) #define GPU_TYPE double #elif defined (CUBLAS) #define GPU_TYPE double #elif defined (KBLAS) #define GPU_TYPE double #elif defined (MAGMA) #define GPU_TYPE double #elif defined (CULA) #define GPU_TYPE double #elif defined (ASPEN) #define GPU_TYPE double #endif #define MAKE_GPU_TYPE(x) (x) #define GPU_TYPE_TO_DOUBLE(x) (x) #define MAKE_GPU_TYPE_REAL(r) (r) // COPY #define CBLAS_COPY cblas_dcopy #define MBLASQD_COPY Rcopy #define MBLASMPFR_COPY Rcopy #define MUBLAS_COPY mublasDXcopy #define CUBLAS_COPY cublasDcopy #define MAGMA_COPY magmablas_dcopy #define CULA_COPY culaDeviceDcopy #define KBLAS_COPY kblas_dcopy // SCAL #define CBLAS_SCAL cblas_dscal #define MBLASQD_SCAL Rscal #define MBLASMPFR_SCAL Rscal #define MUBLAS_SCAL mublasDXscal #define CUBLAS_SCAL cublasDscal #define MAGMA_SCAL #define CULA_SCAL #define KBLAS_SCAL // AXPY #define CBLAS_AXPY cblas_daxpy #define MBLASQD_AXPY Raxpy #define MBLASMPFR_AXPY Raxpy #define MUBLAS_AXPY mublasDXaxpy #define CUBLAS_AXPY cublasDaxpy #define MAGMA_AXPY magmablas_daxpy #define CULA_AXPY culaDeviceDaxpy #define KBLAS_AXPY kblas_daxpy // DOT #define CBLAS_DOT cblas_ddot #define MBLASQD_DOT Rdot #define MBLASMPFR_DOT Rdot #define MUBLAS_DOT mublasDXdot #define CUBLAS_DOT cublasDdot #define MAGMA_DOT magmablas_ddot #define CULA_DOT culaDeviceDdot #define KBLAS_DOT kblas_ddot // GEMV #define MUBLAS_GEMV_MGPU_ASYNC mublasDXgemvMgpuAsync #define MUBLAS_GEMV_MGPU mublasDXgemvMgpu #define CBLAS_GEMV cblas_dgemv #define MBLASQD_GEMV Rgemv #define MBLASMPFR_GEMV Rgemv #define MUBLAS_GEMV mublasDXgemv #define CUBLAS_GEMV cublasDgemv #define MAGMA_GEMV magmablas_dgemv #define CULA_GEMV culaDeviceDgemv #define KBLAS_GEMV kblas_dgemv #define ASPEN_GEMV ASPEN_dgemv // SYMV #define CBLAS_SYMV cblas_dsymv #define MBLASQD_SYMV Rsymv #define MBLASMPFR_SYMV Rsymv #define MUBLAS_SYMV mublasDXsymv #define CUBLAS_SYMV cublasDsymv #define MAGMA_SYMV magmablas_dsymv #define CULA_SYMV culaDeviceDsymv #define KBLAS_SYMV kblas_dsymv #define ASPEN_SYMV ASPEN_dsymv // TRMV #define CBLAS_TRMV cblas_dtrmv #define MBLASQD_TRMV Rtrmv #define MBLASMPFR_TRMV Rtrmv #define MUBLAS_TRMV mublasDXtrmv #define CUBLAS_TRMV cublasDtrmv #define MAGMA_TRMV magmablas_dtrmv #define CULA_TRMV culaDeviceDtrmv #define KBLAS_TRMV #define ASPEN_TRMV // TRSV #define CBLAS_TRSV cblas_dtrsv #define MBLASQD_TRSV Rtrsv #define MBLASMPFR_TRSV Rtrsv #define MUBLAS_TRSV mublasDXtrsv #define CUBLAS_TRSV cublasDtrsv #define MAGMA_TRSV magmablas_dtrsv #define CULA_TRSV culaDeviceDtrsv #define KBLAS_TRSV #define ASPEN_TRSV // GEMM #define CBLAS_GEMM cblas_dgemm #define MBLASQD_GEMM Rgemm #define MBLASMPFR_GEMM Rgemm #define MUBLAS_GEMM mublasDXgemm #define CUBLAS_GEMM cublasDgemm #define CUBLAS_GEMM_MGPU cublasXtDgemm #define MAGMA_GEMM magmablas_dgemm #define CULA_GEMM culaDeviceDgemm #define KBLAS_GEMM #define ASPEN_GEMM // NRM2 #define CUBLAS_NRM cublasDnrm2 #define CBLAS_NRM cblas_dnrm2 #define MBLASQD_NRM Rnrm2 #define MBLASMPFR_NRM Rnrm2 // GER #define CBLAS_GER cblas_dger #define MBLASQD_GER Rger #define MBLASMPFR_GER Rger #define MUBLAS_GER #define CUBLAS_GER cublasDger #define MAGMA_GER magmablas_dger #define CULA_GER culaDeviceDger #define KBLAS_GER #define ASPEN_GER // CSRMV #define MUBLAS_CSRMV mublasDXcsrmv #define CUBLAS_CSRMV cusparseDcsrmv // HYBMV #define CUBLAS_HYBMV cusparseDhybmv #define SPARSE_FORMAT_CONVERT_FROM_SCR cusparseDcsr2hyb // GEAM #define MUBLAS_GEAM mublasDXgeam #define CUBLAS_GEAM cublasDgeam #endif #endif blas_dot2_v01a/testing/testing_common.cpp000644 000765 000024 00000032445 13532137715 022010 0ustar00mukunokistaff000000 000000 // ----- testing handler --------------------------------------------------------------- struct testingHandle_t { // device parameter (single GPU only) cudaDeviceProp devprop; uint32_t devno; int32_t cc; double device_bytes_per_sec; double device_flops_per_sec_sp; double device_flops_per_sec_dp; int32_t Cores; int32_t DPCores; // testing parameter char mode; // c=check, p=perf double routine_flops; double routine_bytes; size_t TxStatic; size_t TyStatic; int32_t driverVersion; int32_t runtimeVersion; int32_t nodisp; int32_t iter; // dim size_t dim_start; size_t dim_stop; size_t dim_step; size_t dim_m_const; size_t dim_n_const; size_t dim_k_const; size_t dim_m_dev; size_t dim_n_dev; size_t dim_k_dev; size_t dim_m_hst; size_t dim_n_hst; size_t dim_k_hst; size_t incx; size_t incy; size_t lda_dev; size_t ldb_dev; size_t ldc_dev; uint32_t dim_step_mode; cublasPointerMode_t pmode; // options char tranA; // N, T, C char tranB; // N, T, C char mtx_file[256]; }; // ----- CUBLAS const value function --------------------------------------------------------------- inline cublasOperation_t cublas_trans_const_m (char tran) { if (tran == 'N' || tran == 'n') return CUBLAS_OP_N; if (tran == 'T' || tran == 't') return CUBLAS_OP_T; if (tran == 'C' || tran == 'c') return CUBLAS_OP_C; return CUBLAS_OP_N; //default } inline cusparseOperation_t cusparse_trans_const_m (char tran) { if (tran == 'N' || tran == 'n') return CUSPARSE_OPERATION_NON_TRANSPOSE; if (tran == 'T' || tran == 't') return CUSPARSE_OPERATION_TRANSPOSE; if (tran == 'C' || tran == 'c') return CUSPARSE_OPERATION_CONJUGATE_TRANSPOSE; return CUSPARSE_OPERATION_NON_TRANSPOSE; //default } void get_routine_theoretial_performance (testingHandle_t *th) { size_t s = sizeof(GPU_TYPE); size_t n = th->dim_n_dev; size_t m = th->dim_m_dev; size_t k = th->dim_k_dev; th->routine_flops = (double) ROUTINE_FLOPS (m, n, k); th->routine_bytes = (double) ROUTINE_BYTES (m, n, k, s); } void dim_hst_setup (testingHandle_t *th) { th->dim_m_hst = th->dim_stop; th->dim_n_hst = th->dim_stop; th->dim_k_hst = th->dim_stop; if (th->dim_m_const > 0) th->dim_m_hst = th->dim_m_const; if (th->dim_n_const > 0) th->dim_n_hst = th->dim_n_const; if (th->dim_k_const > 0) th->dim_k_hst = th->dim_k_const; } void dim_dev_setup (testingHandle_t *th) { th->dim_m_dev = th->dim_start; th->dim_n_dev = th->dim_start; th->dim_k_dev = th->dim_start; if (th->dim_m_const > 0) th->dim_m_dev = th->dim_m_const; if (th->dim_n_const > 0) th->dim_n_dev = th->dim_n_const; if (th->dim_k_const > 0) th->dim_k_dev = th->dim_k_const; } void dim_dev_increment (testingHandle_t *th) { if (th->dim_m_const == 0) { switch (th->dim_step_mode) { case 1: th->dim_m_dev *= 10; break; case 2: th->dim_m_dev *= 2; break; default: th->dim_m_dev += th->dim_step; break; } } if (th->dim_n_const == 0) { switch (th->dim_step_mode) { case 1: th->dim_n_dev *= 10; break; case 2: th->dim_n_dev *= 2; break; default: th->dim_n_dev += th->dim_step; break; } } if (th->dim_k_const == 0) { switch (th->dim_step_mode) { case 1: th->dim_k_dev *= 10; break; case 2: th->dim_k_dev *= 2; break; default: th->dim_k_dev += th->dim_step; break; } } } __inline__ double gettime () { struct timeval tv; cudaDeviceSynchronize (); gettimeofday (&tv, NULL); return tv.tv_sec + (double) tv.tv_usec * 1.0e-6; } int32_t get_num_sp_cores (int32_t cc) { switch (cc) { case 600: return 64; case 610: return 128; case 620: return 128; case 700: return 64; default: printf ("error: unknown architecture\n"); return 0; } } int32_t get_num_dp_cores (int32_t cc) { switch (cc) { case 600: return 32; case 610: return 4; case 620: return 4; case 700: return 32; default: printf ("error: unknown architecture\n"); return 0; } } void dev_setting (testingHandle_t *th) { int32_t driverVersion = 0; int32_t runtimeVersion = 0; int32_t devcnt; cudaGetDeviceCount (&devcnt); cudaDeviceProp devprop; cudaDriverGetVersion(&driverVersion); cudaRuntimeGetVersion(&runtimeVersion); th->driverVersion = driverVersion; th->runtimeVersion = runtimeVersion; cudaSetDevice (th->devno); cudaGetDeviceProperties (&devprop, th->devno); th->devprop = devprop; th->cc = devprop.major * 100 + devprop.minor * 10; th->Cores = get_num_sp_cores (th->cc); th->DPCores = get_num_dp_cores (th->cc); th->device_bytes_per_sec = (double)th->devprop.memoryClockRate * 2. * 1000. * (double)th->devprop.memoryBusWidth / 8.; th->device_flops_per_sec_sp = (double)th->devprop.clockRate * 1000. * 2. * (double)th->devprop.multiProcessorCount * th->Cores; th->device_flops_per_sec_dp = (double)th->devprop.clockRate * 1000. * 2. * (double)th->devprop.multiProcessorCount * th->DPCores; } void testingCreate (int32_t argc, char **argv, testingHandle_t *th) { // default --------------------------- th->devno = 0; th->mode = 'c'; // options th->tranA = 'N'; th->tranB = 'N'; th->nodisp = 0; th->dim_start = 128; th->dim_stop = 1024; th->dim_step = 128; th->dim_m_dev = 0; th->dim_n_dev = 0; th->dim_k_dev = 0; th->dim_m_hst = 0; th->dim_n_hst = 0; th->dim_k_hst = 0; th->dim_m_const = 0; th->dim_n_const = 0; th->dim_k_const = 0; th->incx = 1; th->incy = 1; th->lda_dev = 0; th->ldb_dev = 0; th->ldc_dev = 0; th->dim_step_mode = 0; th->iter = 1; th->TxStatic = 0; th->TyStatic = 0; strcpy (th->mtx_file, ""); th->pmode = CUBLAS_POINTER_MODE_VALUE; // args --------------------------- int32_t opt, opt_index; optind = 1; struct option long_options[] = { {"mtx", required_argument, NULL, 'f'}, {"devno", required_argument, NULL, 'g'}, {"iter", required_argument, NULL, 'i'}, {"mnk", required_argument, NULL, 'j'}, {"k", required_argument, NULL, 'k'}, {"m", required_argument, NULL, 'm'}, {"n", required_argument, NULL, 'n'}, {"mode", required_argument, NULL, 'o'}, {"range", required_argument, NULL, 'r'}, {"nodisp", required_argument, NULL, 'w'}, {0, 0, 0, 0} }; while ((opt = getopt_long (argc, argv, "fgijkmnorw", long_options, &opt_index)) != -1){ switch (opt) { case 'f':{ strcpy (th->mtx_file, optarg); break; } case 'g':{ th->devno = atoi(optarg); break; } case 'i':{ th->iter = atoi(optarg); break; } case 'j':{ th->dim_start = atoi (optarg); th->dim_stop = atoi (optarg); th->dim_step = 1; break; } case 'k':{ th->dim_k_const = (size_t)atoi(optarg); break; } case 'm':{ th->dim_m_const = (size_t)atoi(optarg); break; } case 'n':{ th->dim_n_const = (size_t)atoi(optarg); break; } case 'o':{ th->mode = optarg[0]; break; } case 'r':{ char *str, *c_start, *c_stop, *c_step; char par[] = ":"; str = optarg; c_start = strtok (str, par); c_stop = strtok (NULL, par); c_step = strtok (NULL, par); th->dim_start = atoi (c_start); th->dim_stop = atoi (c_stop); if (strcmp (c_step, "pow") == 0) th->dim_step_mode = 2; else th->dim_step = atoi (c_step); break; } case 'w':{ th->nodisp = atoi(optarg); break; } } } dev_setting (th); } #if defined (MUBLAS) void set_mublas_handler (testingHandle_t *th, mublasHandle_t *mh) { mh->TxStatic = th->TxStatic; mh->TyStatic = th->TyStatic; mh->pmode = th->pmode; } #endif void mublasInitMatRand (size_t rd, size_t cd, size_t ld, GPU_TYPE *mat) { size_t i, j; if (ld == 0) ld = rd; for (j = 0; j < cd; j++) { for (i = 0; i < rd; i++) mat[j*ld+i] = (GPU_TYPE)(rand()/((double)RAND_MAX+1.)); } } void mublasInitMat (size_t rd, size_t cd, size_t ld, GPU_TYPE *mat, GPU_TYPE val) { size_t i, j; if (ld == 0) ld = rd; for (j = 0; j < cd; j++) { for (i = 0; i < rd; i++) mat[j*ld+i] = val; } } void mublasConvert2D (size_t rd, size_t cd, size_t ld, GPU_TYPE *src, mpreal *dst) { size_t i, j; if (ld == 0) ld = rd; for (j = 0; j < cd; j++) { for (i = 0; i < rd; i++) mpfr_set_d (dst[j*ld+i], src[j*ld+i], MPFR_RNDN); } } // check routine (|trg-ref|/|ref|) ------------------------------------------------- void mublasCheckMatrix (size_t m, size_t n, GPU_TYPE *target, size_t ldt, mpreal *ref, size_t ldr) { GPU_TYPE target_d, ref_d; GPU_TYPE max = 0.0, val; size_t errcnt = 0; for(size_t j = 0; j < n; j++) { for(size_t i = 0; i < m; i++) { target_d = target[j*ldt+i]; ref_d = mpfr_get_d (ref[j*ldr+i], MPFR_RNDN); // if (target_d != ref_d) printf(" -- [%zd,%zd] ref=%1.3e trg=%1.3e diff=%1.3e\n", j, i, ref_d, target_d, ref_d-target_d); val = fabs ((target_d - ref_d) / ref_d); // printf ("[%lu,%lu] ref=%+1.18e trg=%+1.18e dif=%+1.18e rel=%+1.18e\n", j, i, target_d, ref_d, ref_d-target_d, val); if (max < val) max = val; if (ref_d - target_d != 0) errcnt++; } } if (isinf(abs(max)) || isnan(abs(max))) printf("\terr: inf or nan\t"); else printf("\t%1.6e\t%zd", max, errcnt); } // print routine ------------------------------------------------- void print_routine_name () { #if defined (PREC_S) printf ("S"); #elif defined (PREC_D) printf ("D"); #elif defined (PREC_SX) printf ("SX"); #elif defined (PREC_DX) printf ("DX"); #else printf ("unknown-precision,"); #endif #if defined (DOT) printf ("DOT\n"); #elif defined (GEMV) printf ("GEMV\n"); #elif defined (CSRMV) printf ("CSRMV\n"); #elif defined (GEMM) printf ("GEMM\n"); #else printf ("unknown-routine\n"); #endif } void print_library_name () { #if defined (CUBLAS) printf ("CUBLAS\n"); #elif defined (MUBLAS) printf ("MUBLAS\n"); #else printf ("unknown-library\n"); #endif } #include void print_info1 (testingHandle_t *th) { if (!th->nodisp) { system("echo -n '# Testing info -----------------------------\n'"); system("echo -n '# \tDate:\t'; date"); system("echo -n '# \tCPU:'; cat /proc/cpuinfo | grep 'model name' | head -n 1"); system("echo -n '# \tOS:\t'; uname -a"); system("echo -n '# \tHost:\t'; hostname"); printf("# \tDevice[%d]\t%s\n", th->devno, th->devprop.name); printf("# \t- Theoretical Peak Memory Bandwidth:\t%3.1f [GB/s]\n", th->device_bytes_per_sec * 1.e-9); printf("# \t- Theoretical Peak Performance (SP):\t%4.1f [GFlops]\n", th->device_flops_per_sec_sp * 1.e-9); printf("# \t- Theoretical Peak Performance (DP):\t%4.1f [GFlops]\n", th->device_flops_per_sec_dp * 1.e-9); printf("# \t- Total Gmem:\t%4.1f [GB]\n", th->devprop.totalGlobalMem * 1e-9); printf("# \t- CC:\t%d.%d\n", th->devprop.major, th->devprop.minor); printf("# \t- ECC Enabled:\t%d\n", th->devprop.ECCEnabled); printf("# \t- MultiProcessorCount:\t%d\n", th->devprop.multiProcessorCount); printf("# \tDriver / Runtime:\t%d, %d\n", th->driverVersion, th->runtimeVersion); printf ("#\tRoutine:\t"); print_routine_name (); printf ("#\tLibrary:\t"); print_library_name (); if (th->mode == 'c') { printf ("#\tmode: checking with "); printf ("MBLASMPFR with %zd-bit\n", mpfr_get_default_prec()); } else { printf ("#\tmode: performance evaluation\n"); } printf ("#\t# of Iter:\t%d\n", th->iter); printf ("# BLAS parameter ---------------------------\n"); printf ("#\ttranA:\t%c\n", th->tranA); printf ("#\ttranB:\t%c\n", th->tranB); if (th->pmode) printf ("#\tcublaspointer:\tDEVICE\n"); else printf ("#\tcublaspointer:\tHOST\n"); } } void print_info2 (testingHandle_t *th) { if (!th->nodisp) { printf ("# Evaluation result ------------------------\n"); printf ("# M\tN\tK"); if (th->mode == 'p') printf ("\tTime[sec]\tPerf[GOps/s]\tPerf[GB/s]\t#ofItr\tEnergy[J]\tPower[W]\t[GOps/W]\tDevName"); else printf ("\tERROR\t#ofERROR"); printf ("\n"); } } ///* #if defined (MUBLAS) void print_mublas_info1 (testingHandle_t *th, mublasHandle_t *mh) { printf ("\t%zd\t%zd\t%zd\t%1.3f\t%zd\t%zd\t%1.3f\t%1.3f\t%1.3f\t%d", (size_t)mh->Tx, (size_t)mh->Ty, (size_t)(mh->Tx*mh->Ty), (float)mh->Ty/(float)mh->Tx, (size_t)mh->Bx, (size_t)mh->By, (float)mh->WrpOcp, (float)mh->BlkOcp, (float)mh->GrdOcp, (int32_t)mh->BlkPerMpMax); } void print_mublas_info2 (testingHandle_t *th, mublasHandle_t *mh) { if (!th->nodisp) { printf ("# ------------------------------------------\n"); printf ("# MUBLAS info (last called) ----------------\n"); printf ("# \tbinaryVersion\t%d\n", mh->funcatb.binaryVersion); printf ("# \tconstSizeBytes\t%zd\n", mh->funcatb.constSizeBytes); printf ("# \tlocalSizeBytes\t%zd\n", mh->funcatb.localSizeBytes); printf ("# \tmaxThreadsPerBlock\t%d\n", mh->funcatb.maxThreadsPerBlock); printf ("# \tnumRegs\t%d\n", mh->funcatb.numRegs); printf ("# \tptxVersion\t%d\n", mh->funcatb.ptxVersion); printf ("# \tShmPerBlkMax\t%d\n", mh->ShmPerBlkMax); printf ("# ------------------------------------------\n"); printf ("# \tTxStatic\t%zd\n", (size_t)mh->TxStatic); printf ("# \tTyStatic\t%zd\n", (size_t)mh->TyStatic); printf ("# ------------------------------------------\n"); printf ("# \tThMin\t%zd\n", (size_t)mh->ThMin); printf ("# \tThMax\t%zd\n", (size_t)mh->ThMax); printf ("# \tThStep\t%zd\n", (size_t)mh->ThStep); printf ("# \tTxMin\t%zd\n", (size_t)mh->TxMin); printf ("# \tTxMax\t%zd\n", (size_t)mh->TxMax); printf ("# \tTxStep\t%zd\n", (size_t)mh->TxStep); printf ("# ------------------------------------------\n"); printf ("# \tWrpOcpSuf\t%1.4f\n", mh->WrpOcpSuf); printf ("# \tBlkOcpSuf\t%1.4f\n", mh->BlkOcpSuf); printf ("# \tGrdOcpSuf\t%1.4f\n", mh->GrdOcpSuf); printf ("# \tTyPerTxMax\t%f\n", mh->TyPerTxMax); printf ("# ------------------------------------------\n"); } } #endif //*/ blas_dot2_v01a/testing/prec_d.h000644 000765 000024 00000011475 13531160667 017665 0ustar00mukunokistaff000000 000000 #ifndef PREC_D_H #define PREC_D_H #ifdef PREC_D #define FPADDCOUNT 1 #define FPMULCOUNT 1 #define FPMADCOUNT 2 // TYPE #define CUBLAS_TYPE double #define CUBLAS_BASETYPE CUBLAS_TYPE #define CUBLAS_ZERO 0. #define CUBLAS_ONE 1. #define CUBLAS_NEGONE -1. #define CBLAS_TYPE double #define CBLAS_BASETYPE CBLAS_TYPE #define CBLAS_ZERO 0. #define CBLAS_ONE 1. #define CBLAS_NEGONE -1. #define MBLASQD_TYPE qd_real #define MBLASQD_BASETYPE MBLASQD_TYPE #define MBLASQD_ZERO qd_real(0.) #define MBLASQD_ONE qd_real(1.) #define MBLASQD_NEGONE qd_real(-1.) #define MBLASMPFR_TYPE mpreal #define MBLASMPFR_BASETYPE MBLASMPFR_TYPE #define MBLASMPFR_ZERO 0. #define MBLASMPFR_ONE 1. #define MBLASMPFR_NEGONE -1. #if defined (MUBLAS) #define GPU_TYPE double #elif defined (CUBLAS) #define GPU_TYPE double #elif defined (KBLAS) #define GPU_TYPE double #elif defined (MAGMA) #define GPU_TYPE double #elif defined (CULA) #define GPU_TYPE double #elif defined (ASPEN) #define GPU_TYPE double #elif defined (MUBLASEX) #define GPU_TYPE double #elif defined (CUOZBLAS) #define GPU_TYPE double #elif defined (OZBLAS) #define GPU_TYPE double #endif #define MAKE_GPU_TYPE(x) (x) #define GPU_TYPE_TO_DOUBLE(x) (x) //#define MAKE_GPU_TYPE_REAL(r) (r) // COPY #define CBLAS_COPY cblas_dcopy #define MBLASQD_COPY Rcopy #define MBLASMPFR_COPY Rcopy #define MUBLAS_COPY mublasDcopy #define CUBLAS_COPY cublasDcopy #define MAGMA_COPY magmablas_dcopy #define CULA_COPY culaDeviceDcopy #define KBLAS_COPY kblas_dcopy // SCAL #define CBLAS_SCAL cblas_dscal #define MBLASQD_SCAL Rscal #define MBLASMPFR_SCAL Rscal #define MUBLAS_SCAL mublasDscal #define CUBLAS_SCAL cublasDscal #define MAGMA_SCAL #define CULA_SCAL #define KBLAS_SCAL // AXPY #define CBLAS_AXPY cblas_daxpy #define MBLASQD_AXPY Raxpy #define MBLASMPFR_AXPY Raxpy #define MUBLAS_AXPY mublasDaxpy #define CUBLAS_AXPY cublasDaxpy #define MAGMA_AXPY magmablas_daxpy #define CULA_AXPY culaDeviceDaxpy #define KBLAS_AXPY kblas_daxpy // DOT #define CBLAS_DOT cblas_ddot #define MBLASQD_DOT Rdot #define MBLASMPFR_DOT Rdot #define MUBLAS_DOT mublasDdot #define MUBLASEX_DOT mublasEXDdot #define CUBLAS_DOT cublasDdot #define MAGMA_DOT magmablas_ddot #define CULA_DOT culaDeviceDdot #define KBLAS_DOT kblas_ddot #define CUOZBLAS_DOT cuozblasDdot // ASUM #define CBLAS_ASUM cblas_dasum #define MBLASQD_ASUM Rasum #define MBLASMPFR_ASUM Rasum #define MUBLAS_ASUM mublasDasum #define CUBLAS_ASUM cublasDasum #define MAGMA_ASUM magmablas_dasum #define CULA_ASUM culaDeviceDasum #define KBLAS_ASUM kblas_dasum // GEMV #define MUBLAS_GEMV_MGPU_ASYNC mublasDgemvMgpuAsync #define MUBLAS_GEMV_MGPU mublasDgemvMgpu #define CBLAS_GEMV cblas_dgemv #define MBLASQD_GEMV Rgemv #define MBLASMPFR_GEMV Rgemv #define MUBLAS_GEMV mublasDgemv #define MUBLASEX_GEMV mublasEXDgemv #define CUBLAS_GEMV cublasDgemv #define MAGMA_GEMV magmablas_dgemv #define CULA_GEMV culaDeviceDgemv #define KBLAS_GEMV kblas_dgemv #define ASPEN_GEMV ASPEN_dgemv #define CUOZBLAS_GEMV cuozblasDgemv // SYMV #define CBLAS_SYMV cblas_dsymv #define MBLASQD_SYMV Rsymv #define MBLASMPFR_SYMV Rsymv #define MUBLAS_SYMV mublasDsymv #define CUBLAS_SYMV cublasDsymv #define MAGMA_SYMV magmablas_dsymv #define CULA_SYMV culaDeviceDsymv #define KBLAS_SYMV kblas_dsymv #define ASPEN_SYMV ASPEN_dsymv // TRMV #define CBLAS_TRMV cblas_dtrmv #define MBLASQD_TRMV Rtrmv #define MBLASMPFR_TRMV Rtrmv #define MUBLAS_TRMV mublasDtrmv #define CUBLAS_TRMV cublasDtrmv #define MAGMA_TRMV magmablas_dtrmv #define CULA_TRMV culaDeviceDtrmv #define KBLAS_TRMV #define ASPEN_TRMV // TRSV #define CBLAS_TRSV cblas_dtrsv #define MBLASQD_TRSV Rtrsv #define MBLASMPFR_TRSV Rtrsv #define MUBLAS_TRSV mublasDtrsv #define CUBLAS_TRSV cublasDtrsv #define MAGMA_TRSV magmablas_dtrsv #define CULA_TRSV culaDeviceDtrsv #define KBLAS_TRSV #define ASPEN_TRSV // GEMM #define CBLAS_GEMM cblas_dgemm #define MBLASQD_GEMM Rgemm #define MBLASMPFR_GEMM Rgemm #define MUBLAS_GEMM mublasDgemm #define CUBLAS_GEMM cublasDgemm #define CUBLAS_GEMM_MGPU cublasXtDgemm #define CUBLAS_GEMM_BATCHED cublasDgemmBatched #define MAGMA_GEMM magmablas_dgemm #define CULA_GEMM culaDeviceDgemm #define KBLAS_GEMM #define ASPEN_GEMM #define CUOZBLAS_GEMM cuozblasDgemm // NRM2 #define CUBLAS_NRM cublasDnrm2 #define CBLAS_NRM cblas_dnrm2 #define MBLASQD_NRM Rnrm2 #define MBLASMPFR_NRM Rnrm2 // GER #define CBLAS_GER cblas_dger #define MBLASQD_GER Rger #define MBLASMPFR_GER Rger #define MUBLAS_GER #define CUBLAS_GER cublasDger #define MAGMA_GER magmablas_dger #define CULA_GER culaDeviceDger #define KBLAS_GER #define ASPEN_GER // CSRMV #define MUBLAS_CSRMV mublasDcsrmv #define MUBLASEX_CSRMV mublasEXDcsrmv #define CUBLAS_CSRMV cusparseDcsrmv #define CUOZBLAS_CSRMV cuozblasDcsrmv // HYBMV #define CUBLAS_HYBMV cusparseDhybmv #define SPARSE_FORMAT_CONVERT_FROM_SCR cusparseDcsr2hyb // GEAM #define MUBLAS_GEAM mublasDgeam #define CUBLAS_GEAM cublasDgeam #endif #endif blas_dot2_v01a/testing/testing_level2.cpp000644 000765 000024 00000013761 13532473335 021712 0ustar00mukunokistaff000000 000000 #define ROUTINE_FLOPS(m,n,k) (2*m*n+3*m) #define ROUTINE_BYTES(m,n,k,s) ((2*m+n+m*n)*s) #include "testing_common.h" #include "testing_common.cpp" #if defined (MUBLAS) #define ROUTINE_TARGET(ha,th,m,n,al,A,lda,X,bt,Y) MUBLAS_GEMV(&ha,th.tranA,m,n,&al,A,lda,X,th.incx,&bt,Y,th.incy) #elif defined (CUBLAS) #define ROUTINE_TARGET(ha,th,m,n,al,A,lda,X,bt,Y) CUBLAS_GEMV(ha,cublas_trans_const_m(th.tranA),m,n,&al,A,lda,X,th.incx,&bt,Y,th.incy) #endif int32_t main (int32_t argc, char **argv) { size_t i; size_t lda_dev, lda_hst; size_t cda_dev, cda_hst; size_t rda_dev, rda_hst; size_t vlx_dev, vlx_hst; size_t vly_dev, vly_hst; double t0, t1; mpfr_set_default_prec(MPFR_PREC); mpreal::set_default_prec(MPFR_PREC); // testing setup ------------------------------ testingHandle_t th; testingCreate (argc, argv, &th); print_info1 (&th); // -------------------------------------------- // library setup ------------------------------ unsigned long long energy0, energy1; nvmlDevice_t nvmldev; nvmlInit(); nvmlDeviceGetHandleByIndex(1, &nvmldev); char devname[256]; nvmlDeviceGetName(nvmldev, devname, 256); #if defined (MUBLAS) mublasHandle_t ha; mublasCreate (&ha); set_mublas_handler (&th, &ha); #elif defined (CUBLAS) cublasHandle_t ha; cublasCreate (&ha); cublasSetPointerMode(ha, CUBLAS_POINTER_MODE_VALUE); #endif // -------------------------------------------- // memory setup ------------------------------- dim_hst_setup (&th); rda_hst = th.dim_stop; cda_hst = th.dim_stop; vlx_hst = th.dim_stop; vly_hst = th.dim_stop; if (th.tranA == 'N' || th.tranA == 'n') { if (th.dim_n_const > 0) vlx_hst = th.dim_n_const; if (th.dim_m_const > 0) vly_hst = th.dim_m_const; } else { if (th.dim_m_const > 0) vlx_hst = th.dim_m_const; if (th.dim_n_const > 0) vly_hst = th.dim_n_const; } if (th.dim_m_const > 0) rda_hst = th.dim_m_const; if (th.dim_n_const > 0) cda_hst = th.dim_n_const; lda_hst = rda_hst; // malloc host memory GPU_TYPE alpha, beta; GPU_TYPE *hst_A = new GPU_TYPE[lda_hst * cda_hst]; GPU_TYPE *hst_X = new GPU_TYPE[vlx_hst * th.incx]; GPU_TYPE *hst_Y = new GPU_TYPE[vly_hst * th.incy]; GPU_TYPE *hst_Y_t = new GPU_TYPE[vly_hst * th.incy]; // initialize mublasInitMat (1, 1, 0, &alpha, 1.); mublasInitMat (1, 1, 0, &beta, 0.); mublasInitMatRand (lda_hst, cda_hst, lda_hst, hst_A); mublasInitMatRand (vlx_hst * th.incx, 1, 0, hst_X); mublasInitMat (vly_hst * th.incy, 1, 0, hst_Y, 0.); // -------------------------------------------- print_info2 (&th); // evaluation --------------------------------- dim_dev_setup (&th); while (1) { if ((th.dim_m_const == 0 && th.dim_m_dev > th.dim_stop) || (th.dim_n_const == 0 && th.dim_n_dev > th.dim_stop)) break; // dim setup if (th.tranA == 'N' || th.tranA == 'n') { vlx_dev = th.dim_n_dev; vly_dev = th.dim_m_dev; } else { vlx_dev = th.dim_m_dev; vly_dev = th.dim_n_dev; } rda_dev = th.dim_m_dev; cda_dev = th.dim_n_dev; // malloc device memory GPU_TYPE *dev_A, *dev_X, *dev_Y; size_t pitch; cudaMallocPitch ((void **) &dev_A, &pitch, sizeof(GPU_TYPE) * rda_dev, cda_dev); lda_dev = pitch/sizeof(GPU_TYPE); cudaMalloc ((void **) &dev_X, sizeof(GPU_TYPE) * vlx_dev * th.incx); cudaMalloc ((void **) &dev_Y, sizeof(GPU_TYPE) * vly_dev * th.incy); // memcpy from hst to device cublasSetMatrix (rda_dev, cda_dev, sizeof(GPU_TYPE), hst_A, lda_hst, dev_A, lda_dev); cublasSetVector (vlx_dev * th.incx, sizeof(GPU_TYPE), hst_X, 1, dev_X, 1); cublasSetVector (vly_dev * th.incy, sizeof(GPU_TYPE), hst_Y, 1, dev_Y, 1); // --------------------------------------------- printf ("%zd\t%zd\t--", (size_t)th.dim_m_dev, (size_t)th.dim_n_dev); get_routine_theoretial_performance (&th); // execution --------------------------------- if (th.mode == 'p') { // warm up for (i = 0; i < WarmUpLoop; i++) ROUTINE_TARGET(ha,th,th.dim_m_dev,th.dim_n_dev,alpha,dev_A,lda_dev,dev_X,beta,dev_Y); nvmlDeviceGetTotalEnergyConsumption (nvmldev, &energy0); t0 = gettime (); for (i = 0; i < th.iter; i++) ROUTINE_TARGET(ha,th,th.dim_m_dev,th.dim_n_dev,alpha,dev_A,lda_dev,dev_X,beta,dev_Y); t1 = gettime (); nvmlDeviceGetTotalEnergyConsumption (nvmldev, &energy1); double sec = (t1 - t0) / (double)th.iter; double joules = (energy1 - energy0)*1.e-3 / (double)th.iter; double watt = joules / sec; double gfpw = (th.routine_flops) * 1.0e-9 / joules; printf ("\t%1.3e\t%1.3e\t%1.3e\t%zd", sec, (th.routine_flops / sec) * 1.0e-9, (th.routine_bytes / sec) * 1.0e-9, (size_t)th.iter); printf ("\t%1.3e\t%1.3e\t%1.3e\t(%s)", joules, watt, gfpw, devname); } if (th.mode == 'c') { ROUTINE_TARGET(ha,th,th.dim_m_dev,th.dim_n_dev,alpha,dev_A,lda_dev,dev_X,beta,dev_Y); } // ------------------------------------------- if (th.mode == 'c') cublasGetVector (vly_dev * th.incy, sizeof(GPU_TYPE), dev_Y, 1, hst_Y_t, 1); cudaFree (dev_A); cudaFree (dev_X); cudaFree (dev_Y); if (th.mode == 'c') { mpreal alpha_r = 0; mpreal beta_r = 0; mpreal *hst_A_r = new mpreal[lda_hst * cda_dev]; mpreal *hst_X_r = new mpreal[vlx_dev * th.incx]; mpreal *hst_Y_r = new mpreal[vly_dev * th.incy]; mublasConvert2D (1, 1, 0, &alpha, &alpha_r); mublasConvert2D (1, 1, 0, &beta, &beta_r); mublasConvert2D (rda_dev, cda_dev, lda_hst, hst_A, hst_A_r); mublasConvert2D (vlx_dev * th.incx, 1, 0, hst_X, hst_X_r); mublasConvert2D (vly_dev * th.incy, 1, 0, hst_Y, hst_Y_r); Rgemv (&th.tranA,rda_dev,cda_dev,alpha_r,hst_A_r,lda_hst,hst_X_r,1,beta_r,hst_Y_r,1); mublasCheckMatrix (vly_dev * th.incy, 1, hst_Y_t, vly_dev * th.incy, hst_Y_r, vly_dev * th.incy); delete[]hst_A_r; delete[]hst_X_r; delete[]hst_Y_r; } printf ("\n"); dim_dev_increment (&th); if (th.dim_m_const && th.dim_n_const) break; } // -------------------------------------------- delete[]hst_A; delete[]hst_X; delete[]hst_Y; delete[]hst_Y_t; #if defined (MUBLAS) mublasDestroy (&ha); #elif defined (CUBLAS) cublasDestroy (ha); #endif nvmlShutdown (); // -------------------------------------------- return 0; } blas_dot2_v01a/testing/testing_level3.cpp000644 000765 000024 00000015644 13532473326 021715 0ustar00mukunokistaff000000 000000 #define ROUTINE_FLOPS(m,n,k) (2*m*n*k+3*m*n) #define ROUTINE_BYTES(m,n,k,s) ((m*k+k*n+2*m*n)*s) #include "testing_common.h" #include "testing_common.cpp" #if defined (MUBLAS) #define ROUTINE_TARGET(ha,th,m,n,k,al,A,lda,B,ldb,bt,C,ldc) MUBLAS_GEMM(&ha,th.tranA,th.tranB,m,n,k,&al,A,lda,B,ldb,&bt,C,ldc) #elif defined (CUBLAS) #define ROUTINE_TARGET(ha,th,m,n,k,al,A,lda,B,ldb,bt,C,ldc) CUBLAS_GEMM(ha,cublas_trans_const_m(th.tranA),cublas_trans_const_m(th.tranB),m,n,k,&al,A,lda,B,ldb,&bt,C,ldc) #endif int32_t main (int32_t argc, char **argv) { size_t i; size_t lda_dev, lda_hst, rda_dev, rda_hst, cda_dev, cda_hst; size_t ldb_dev, ldb_hst, rdb_dev, rdb_hst, cdb_dev, cdb_hst; size_t ldc_dev, ldc_hst, rdc_dev, rdc_hst, cdc_dev, cdc_hst; double t0, t1; mpfr_set_default_prec(MPFR_PREC); mpreal::set_default_prec(MPFR_PREC); // testing setup ------------------------------ testingHandle_t th; testingCreate (argc, argv, &th); print_info1 (&th); // -------------------------------------------- // library setup ------------------------------ unsigned long long energy0, energy1; nvmlDevice_t nvmldev; nvmlInit(); nvmlDeviceGetHandleByIndex(1, &nvmldev); char devname[256]; nvmlDeviceGetName(nvmldev, devname, 256); #if defined (MUBLAS) mublasHandle_t ha; mublasCreate (&ha); set_mublas_handler (&th, &ha); #elif defined (CUBLAS) cublasHandle_t ha; cublasCreate (&ha); cublasSetPointerMode(ha, CUBLAS_POINTER_MODE_VALUE); #endif // -------------------------------------------- // memory setup ------------------------------- // dim setup dim_hst_setup (&th); // A rda_hst = th.dim_stop; cda_hst = th.dim_stop; if (th.tranA == 'N' || th.tranA == 'n') { if (th.dim_m_const > 0) rda_hst = th.dim_m_const; if (th.dim_k_const > 0) cda_hst = th.dim_k_const; } else { if (th.dim_k_const > 0) rda_hst = th.dim_k_const; if (th.dim_m_const > 0) cda_hst = th.dim_m_const; } lda_hst = rda_hst; // B rdb_hst = th.dim_stop; cdb_hst = th.dim_stop; if (th.tranB == 'N' || th.tranB == 'n') { if (th.dim_k_const > 0) rdb_hst = th.dim_k_const; if (th.dim_n_const > 0) cdb_hst = th.dim_n_const; } else { if (th.dim_n_const > 0) rdb_hst = th.dim_n_const; if (th.dim_k_const > 0) cdb_hst = th.dim_k_const; } ldb_hst = rdb_hst; // C rdc_hst = th.dim_stop; cdc_hst = th.dim_stop; if (th.dim_m_const > 0) rdc_hst = th.dim_m_const; if (th.dim_n_const > 0) cdc_hst = th.dim_n_const; ldc_hst = rdc_hst; // malloc host memory GPU_TYPE alpha, beta; GPU_TYPE *hst_A = new GPU_TYPE[lda_hst * cda_hst]; GPU_TYPE *hst_B = new GPU_TYPE[ldb_hst * cdb_hst]; GPU_TYPE *hst_C = new GPU_TYPE[ldc_hst * cdc_hst]; GPU_TYPE *hst_C_t = new GPU_TYPE[ldc_hst * cdc_hst]; // initialize mublasInitMat (1, 1, 0, &alpha, 1.); mublasInitMat (1, 1, 0, &beta, 0.); mublasInitMatRand (lda_hst, cda_hst, lda_hst, hst_A); mublasInitMatRand (ldb_hst, cdb_hst, ldb_hst, hst_B); mublasInitMat (ldc_hst, cdc_hst, ldc_hst, hst_C, 0.); // -------------------------------------------- print_info2 (&th); // evaluation --------------------------------- dim_dev_setup (&th); while (1) { if ((th.dim_m_const == 0 && th.dim_m_dev > th.dim_stop) || (th.dim_n_const == 0 && th.dim_n_dev > th.dim_stop) || (th.dim_k_const == 0 && th.dim_k_dev > th.dim_stop)) break; // dim setup // A if (th.tranA == 'N' || th.tranA == 'n') { rda_dev = th.dim_m_dev; cda_dev = th.dim_k_dev; } else { rda_dev = th.dim_k_dev; cda_dev = th.dim_m_dev; } // B if (th.tranB == 'N' || th.tranB == 'n') { rdb_dev = th.dim_k_dev; cdb_dev = th.dim_n_dev; } else { rdb_dev = th.dim_n_dev; cdb_dev = th.dim_k_dev; } // C rdc_dev = th.dim_m_dev; cdc_dev = th.dim_n_dev; // malloc device memory GPU_TYPE *dev_A, *dev_B, *dev_C; size_t pitch; cudaMallocPitch ((void **) &dev_A, &pitch, sizeof(GPU_TYPE) * rda_dev, cda_dev); lda_dev = pitch/sizeof(GPU_TYPE); cudaMallocPitch ((void **) &dev_B, &pitch, sizeof(GPU_TYPE) * rdb_dev, cdb_dev); ldb_dev = pitch/sizeof(GPU_TYPE); cudaMallocPitch ((void **) &dev_C, &pitch, sizeof(GPU_TYPE) * rdc_dev, cdc_dev); ldc_dev = pitch/sizeof(GPU_TYPE); // memcpy from host to device cublasSetMatrix(rda_dev, cda_dev, sizeof(GPU_TYPE), hst_A, lda_hst, dev_A, lda_dev); cublasSetMatrix(rdb_dev, cdb_dev, sizeof(GPU_TYPE), hst_B, ldb_hst, dev_B, ldb_dev); cublasSetMatrix(rdc_dev, cdc_dev, sizeof(GPU_TYPE), hst_C, ldc_hst, dev_C, ldc_dev); printf ("%zd\t%zd\t%zd", (size_t)th.dim_m_dev, (size_t)th.dim_n_dev, (size_t)th.dim_k_dev); get_routine_theoretial_performance (&th); // execution --------------------------------- if (th.mode == 'p') { // warm up for (i = 0; i < WarmUpLoop; i++) ROUTINE_TARGET(ha,th,th.dim_m_dev,th.dim_n_dev,th.dim_k_dev,alpha,dev_A,lda_dev,dev_B,ldb_dev,beta,dev_C,ldc_dev); nvmlDeviceGetTotalEnergyConsumption (nvmldev, &energy0); t0 = gettime (); for (i = 0; i < th.iter; i++) ROUTINE_TARGET(ha,th,th.dim_m_dev,th.dim_n_dev,th.dim_k_dev,alpha,dev_A,lda_dev,dev_B,ldb_dev,beta,dev_C,ldc_dev); t1 = gettime (); nvmlDeviceGetTotalEnergyConsumption (nvmldev, &energy1); double sec = (t1 - t0) / (double)th.iter; double joules = (energy1 - energy0)*1.e-3 / (double)th.iter; double watt = joules / sec; double gfpw = (th.routine_flops) * 1.0e-9 / joules; printf ("\t%1.3e\t%1.3e\t%1.3e\t%zd", sec, (th.routine_flops / sec) * 1.0e-9, (th.routine_bytes / sec) * 1.0e-9, (size_t)th.iter); printf ("\t%1.3e\t%1.3e\t%1.3e\t(%s)", joules, watt, gfpw, devname); } if (th.mode == 'c') { ROUTINE_TARGET(ha,th,th.dim_m_dev,th.dim_n_dev,th.dim_k_dev,alpha,dev_A,lda_dev,dev_B,ldb_dev,beta,dev_C,ldc_dev); } // ------------------------------------------- if (th.mode == 'c') cublasGetMatrix (rdc_dev, cdc_dev, sizeof(GPU_TYPE), dev_C, ldc_dev, hst_C_t, ldc_hst); cudaFree (dev_A); cudaFree (dev_B); cudaFree (dev_C); if (th.mode == 'c') { mpreal alpha_r = 0; mpreal beta_r = 0; mpreal *hst_A_r = new mpreal[lda_hst * cda_hst]; mpreal *hst_B_r = new mpreal[ldb_hst * cdb_hst]; mpreal *hst_C_r = new mpreal[ldc_hst * cdc_hst]; mublasConvert2D (1, 1, 0, &alpha, &alpha_r); mublasConvert2D (1, 1, 0, &beta, &beta_r); mublasConvert2D (rda_dev, cda_dev, lda_hst, hst_A, hst_A_r); mublasConvert2D (rdb_dev, cdb_dev, ldb_hst, hst_B, hst_B_r); mublasConvert2D (rdc_dev, cdc_dev, ldc_hst, hst_C, hst_C_r); Rgemm (&th.tranA,&th.tranB,th.dim_m_dev,th.dim_n_dev,th.dim_k_dev,alpha_r,hst_A_r,lda_hst,hst_B_r,ldb_hst,beta_r,hst_C_r,ldc_hst); mublasCheckMatrix (th.dim_m_dev, th.dim_n_dev, hst_C_t, ldc_hst, hst_C_r, ldc_hst); delete[]hst_A_r; delete[]hst_B_r; delete[]hst_C_r; } printf ("\n"); dim_dev_increment (&th); if (th.dim_m_const && th.dim_n_const && th.dim_k_const) break; } // -------------------------------------------- delete[]hst_A; delete[]hst_B; delete[]hst_C; delete[]hst_C_t; #if defined (MUBLAS) mublasDestroy (&ha); #elif defined (CUBLAS) cublasDestroy (ha); #endif nvmlShutdown (); return 0; } blas_dot2_v01a/testing/testing_level1b.cpp000644 000765 000024 00000007762 13531404070 022044 0ustar00mukunokistaff000000 000000 #define ROUTINE_FLOPS(m,n,k) (2*n) #define ROUTINE_BYTES(m,n,k,s) (2*n*s) #include "testing_common.h" #include "testing_common.cpp" #if defined (MUBLAS) #define ROUTINE_TARGET(ha,th,n,X,Y,r) MUBLAS_DOT(&ha,n,X,th.incx,Y,th.incy,r) #elif defined (CUBLAS) #define ROUTINE_TARGET(ha,th,n,X,Y,r) CUBLAS_DOT(ha,n,X,th.incx,Y,th.incy,r) #endif int32_t main (int32_t argc, char **argv) { size_t i; double t0, t1; mpreal hst_result_r; mpfr_set_default_prec(MPFR_PREC); mpreal::set_default_prec(MPFR_PREC); // testing setup ------------------------------ testingHandle_t th; testingCreate (argc, argv, &th); print_info1 (&th); // -------------------------------------------- // library setup ------------------------------ unsigned long long energy0, energy1; nvmlDevice_t nvmldev; nvmlInit(); nvmlDeviceGetHandleByIndex(1, &nvmldev); char devname[256]; nvmlDeviceGetName(nvmldev, devname, 256); #if defined (MUBLAS) mublasHandle_t ha; mublasCreate (&ha); set_mublas_handler (&th, &ha); #elif defined (CUBLAS) cublasHandle_t ha; cublasCreate (&ha); cublasSetPointerMode(ha, CUBLAS_POINTER_MODE_VALUE); #endif // -------------------------------------------- // memory setup ------------------------------- GPU_TYPE hst_result_t; GPU_TYPE *dev_X, *dev_Y; // dim setup dim_hst_setup (&th); // malloc host memory GPU_TYPE *hst_X = new GPU_TYPE[th.dim_n_hst * th.incx]; GPU_TYPE *hst_Y = new GPU_TYPE[th.dim_n_hst * th.incy]; // initialize mublasInitMatRand (th.dim_n_hst*th.incx, 1, 0, hst_X); mublasInitMatRand (th.dim_n_hst*th.incy, 1, 0, hst_Y); // -------------------------------------------- print_info2 (&th); // evaluation --------------------------------- dim_dev_setup (&th); while (1) { if (th.dim_n_const == 0 && th.dim_n_dev > th.dim_stop) break; cudaMalloc ((void **) &dev_X, sizeof(GPU_TYPE) * th.dim_n_dev * th.incx); cudaMalloc ((void **) &dev_Y, sizeof(GPU_TYPE) * th.dim_n_dev * th.incy); cublasSetVector(th.dim_n_dev * th.incx, sizeof(GPU_TYPE), hst_X, 1, dev_X, 1); cublasSetVector(th.dim_n_dev * th.incy, sizeof(GPU_TYPE), hst_Y, 1, dev_Y, 1); printf ("--\t%zd\t--", (size_t)th.dim_n_dev); get_routine_theoretial_performance (&th); // execution --------------------------------- if (th.mode == 'p') { // warm up for (i = 0; i < WarmUpLoop; i++) ROUTINE_TARGET(ha,th,th.dim_n_dev,dev_X,dev_Y,&hst_result_t); nvmlDeviceGetTotalEnergyConsumption (nvmldev, &energy0); t0 = gettime (); for (i = 0; i < th.iter; i++) ROUTINE_TARGET(ha,th,th.dim_n_dev,dev_X,dev_Y,&hst_result_t); t1 = gettime (); nvmlDeviceGetTotalEnergyConsumption (nvmldev, &energy1); double sec = (t1 - t0) / (double)th.iter; double joules = (energy1 - energy0)*1.e-3 / (double)th.iter; double watt = joules / sec; double gfpw = (th.routine_flops) * 1.0e-9 / joules; printf ("\t%1.3e\t%1.3e\t%1.3e\t%zd", sec, (th.routine_flops / sec) * 1.0e-9, (th.routine_bytes / sec) * 1.0e-9, (size_t)th.iter); printf ("\t%1.3e\t%1.3e\t%1.3e\t(%s)", joules, watt, gfpw, devname); } if (th.mode == 'c') { ROUTINE_TARGET(ha,th,th.dim_n_dev,dev_X,dev_Y,&hst_result_t); } // ------------------------------------------- cudaFree (dev_X); cudaFree (dev_Y); if (th.mode == 'c') { mpreal *hst_X_r = new mpreal[th.dim_n_hst]; mpreal *hst_Y_r = new mpreal[th.dim_n_hst]; mublasConvert2D (th.dim_n_hst*th.incx, 1, 0, hst_X, hst_X_r); mublasConvert2D (th.dim_n_hst*th.incy, 1, 0, hst_Y, hst_Y_r); hst_result_r = Rdot (th.dim_n_dev,hst_X_r,1,hst_Y_r,1); mublasCheckMatrix (1, 1, &hst_result_t, 1, &hst_result_r, 1); delete[]hst_X_r; delete[]hst_Y_r; } printf ("\n"); dim_dev_increment (&th); if (th.dim_m_const && th.dim_n_const && th.dim_k_const) break; } // -------------------------------------------- // shutdown ----------------------------------- delete[]hst_X; delete[]hst_Y; #if defined (MUBLAS) mublasDestroy (&ha); #elif defined (CUBLAS) cublasDestroy (ha); #endif nvmlShutdown (); // -------------------------------------------- return 0; } blas_dot2_v01a/testing/testing_setting.h000644 000765 000024 00000000272 13532474514 021634 0ustar00mukunokistaff000000 000000 #ifndef TESTING_SETTING #define TESTING_SETTING #define SIZE_T size_t #define CUBLAS_POINTER_MODE_VALUE CUBLAS_POINTER_MODE_HOST #define MPFR_PREC 2048 #define WarmUpLoop 3 #endif blas_dot2_v01a/include/mublas.h000644 000765 000024 00000011472 13532136664 017660 0ustar00mukunokistaff000000 000000 #ifndef MUBLAS_H #define MUBLAS_H #if defined(__cplusplus) extern "C" { #endif #include #include #include #include #include #include // struct ---------------------------------- typedef struct { struct cudaDeviceProp devprop; // mublas parameter float *work_addr; float *work_addr2; int32_t pmode; // pointer mode // device parameter int32_t driverVersion; int32_t runtimeVersion; int32_t cc; // architecture parameter uint32_t WrpPerMpPmax; // Physical Max of Warps per Multiprocessor uint32_t BlkPerMpPmax; // Physical Max of Blocks per Multiprocessor uint32_t RegUnit; // Register Allocation Unit uint32_t ShmUnit; // Shared Memory Allocation Unit uint32_t WrpGran; // Warp Allocation Granularity uint32_t Cores; // # of CUDA Cores per Multiprocessor uint32_t DPCores; // # of DP Cores per Multiprocessor // kernel parameters struct cudaFuncAttributes funcatb; void (*func_getShmPerBlk)(void*); void (*func_getBlkPerGrd)(void*); enum cudaFuncCache func_cache; uint32_t N_T; uint32_t BlkDim; float WrpOcp; // Warp Occupancy float BlkOcp; // Block Occupancy float GrdOcp; // Grid Occupancy size_t Bx; size_t By; size_t Bz; uint32_t Tx; uint32_t Ty; uint32_t Tz; size_t m; size_t n; size_t k; uint32_t ShmPerBlk; uint32_t ShmPerBlkMax; uint32_t BlkPerMpMax; uint32_t N_one; uint32_t batchCount; // tuning parameter float WrpOcpSuf; float BlkOcpSuf; float GrdOcpSuf; uint32_t TxMin; uint32_t TxMax; uint32_t TxStatic; uint32_t TyStatic; uint32_t ThMin; uint32_t ThMax; uint32_t TxStep; uint32_t ThStep; float TyPerTxMax; uint32_t TxModTyZero; } mublasHandle_t; // mublas function void mublasCreate (mublasHandle_t*); void mublasSetStream (mublasHandle_t*, cudaStream_t); void mublasDestroy (mublasHandle_t*); // GEMM extern int32_t mublasSgemm (mublasHandle_t*, const char, const char, const size_t, const size_t, const size_t, const float*, const float*, const size_t, const float*, const size_t, const float*, float*, const size_t); extern int32_t mublasDgemm (mublasHandle_t*, const char, const char, const size_t, const size_t, const size_t, const double*, const double*, const size_t, const double*, const size_t, const double*, double*, const size_t); extern int32_t mublasSXgemm (mublasHandle_t*, const char, const char, const size_t, const size_t, const size_t, const float*, const float*, const size_t, const float*, const size_t, const float*, float*, const size_t); extern int32_t mublasDXgemm (mublasHandle_t*, const char, const char, const size_t, const size_t, const size_t, const double*, const double*, const size_t, const double*, const size_t, const double*, double*, const size_t); // GEMV extern int32_t mublasSgemv (mublasHandle_t*, const char, const size_t, const size_t, const float*, const float*, const size_t, const float*, const size_t, const float*, float*, const size_t); extern int32_t mublasDgemv (mublasHandle_t*, const char, const size_t, const size_t, const double*, const double*, const size_t, const double*, const size_t, const double*, double*, const size_t); extern int32_t mublasSXgemv (mublasHandle_t*, const char, const size_t, const size_t, const float*, const float*, const size_t, const float*, const size_t, const float*, float*, const size_t); extern int32_t mublasDXgemv (mublasHandle_t*, const char, const size_t, const size_t, const double*, const double*, const size_t, const double*, const size_t, const double*, double*, const size_t); // DOT extern int32_t mublasSdot (mublasHandle_t*, const size_t, const float*, const size_t, const float*, const size_t, float*); extern int32_t mublasDdot (mublasHandle_t*, const size_t, const double*, const size_t, const double*, const size_t, double*); extern int32_t mublasSXdot (mublasHandle_t*, const size_t, const float*, const size_t, const float*, const size_t, float*); extern int32_t mublasDXdot (mublasHandle_t*, const size_t, const double*, const size_t, const double*, const size_t, double*); // CSRMV extern int32_t mublasScsrmv (mublasHandle_t*, const char, const size_t, const size_t, const size_t, const float*, const float*, const int32_t*, const int32_t*, const float*, const float*, float*); extern int32_t mublasDcsrmv (mublasHandle_t*, const char, const size_t, const size_t, const size_t, const double*, const double*, const int32_t*, const int32_t*, const double*, const double*, double*); extern int32_t mublasSXcsrmv (mublasHandle_t*, const char, const size_t, const size_t, const size_t, const float*, const float*, const int32_t*, const int32_t*, const float*, const float*, float*); extern int32_t mublasDXcsrmv (mublasHandle_t*, const char, const size_t, const size_t, const size_t, const double*, const double*, const int32_t*, const int32_t*, const double*, const double*, double*); #if defined(__cplusplus) } #endif #endif